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authorTristan Gingold <tgingold@free.fr>2019-10-03 19:54:57 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-03 19:54:57 +0200
commit86a93728739ef1dc261856be3935321185736fe9 (patch)
treed1c49fbd784033becb54afbe08fcdf788c9029d2
parenta94d2a0592495f3216c54b63e9591d6af760d999 (diff)
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synth-inference: minor improvement.
-rw-r--r--src/synth/synth-inference.adb19
1 files changed, 9 insertions, 10 deletions
diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb
index 3b055901f..df60f0148 100644
--- a/src/synth/synth-inference.adb
+++ b/src/synth/synth-inference.adb
@@ -251,13 +251,6 @@ package body Synth.Inference is
Data := Get_Driver (I1);
-- Don't try to free driver of I1 as it is reconnected.
Disconnect (I1);
- -- If there is a condition with the clock, that's an enable which
- -- keep the previous value if the condition is false. Add the mux
- -- for it.
- if Enable /= No_Net then
- Data := Build_Mux2 (Ctxt, Enable, Prev_Val, Data);
- Copy_Location (Data, Enable);
- end if;
-- If the signal declaration has an initial value, get it.
Sig := Get_Parent (Prev_Val);
@@ -289,9 +282,7 @@ package body Synth.Inference is
-- The parent must be a mux (it's a chain of muxes).
Mux := Get_Parent (Get_First_Sink (Last_Out));
- if Get_Id (Mux) /= Id_Mux2 then
- raise Internal_Error;
- end if;
+ pragma Assert (Get_Id (Mux) = Id_Mux2);
-- Extract the reset condition and the reset value.
Sel := Get_Driver (Get_Mux2_Sel (Mux));
@@ -327,6 +318,14 @@ package body Synth.Inference is
end loop;
end;
+ -- If there is a condition with the clock, that's an enable which
+ -- keep the previous value if the condition is false. Add the mux
+ -- for it.
+ if Enable /= No_Net then
+ Data := Build_Mux2 (Ctxt, Enable, Prev_Val, Data);
+ Copy_Location (Data, Enable);
+ end if;
+
-- Create the FF.
if Rst = No_Net then
pragma Assert (Rst_Val = No_Net);