synth: minor refactoring in netlists.disp_vhdl

2 files changed, 54 insertions, 47 deletions

diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 1ae79721a..7e254c50a 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -18,7 +18,7 @@
 --  Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
 --  MA 02110-1301, USA.
 
-with Ada.Text_IO; use Ada.Text_IO;
+with Simple_IO; use Simple_IO;
 with Types_Utils; use Types_Utils;
 with Name_Table; use Name_Table;
 with Netlists.Utils; use Netlists.Utils;
@@ -134,52 +134,6 @@ package body Netlists.Disp_Vhdl is
       end if;
    end Put_Interface_Name;
 
-   procedure Disp_Entity (M : Module)
-   is
-      First : Boolean;
-   begin
-      --  Module id and name.
-      Put_Line ("library ieee;");
-      Put_Line ("use ieee.std_logic_1164.all;");
-      Put_Line ("use ieee.numeric_std.all;");
-      New_Line;
-      Put ("entity ");
-      Put_Name (Get_Name (M));
-      Put_Line (" is");
-
-      --  Ports.
-      First := True;
-      for P of Ports_Desc (M) loop
-         if First then
-            Put_Line ("  port (");
-            First := False;
-         else
-            Put_Line (";");
-         end if;
-         Put ("    ");
-         Put_Name (P.Name);
-         Put (" : ");
-         case P.Dir is
-            when Port_In =>
-               Put ("in");
-            when Port_Out =>
-               Put ("out");
-            when Port_Inout =>
-               Put ("inout");
-         end case;
-         Put (' ');
-         Put_Type (P.W);
-      end loop;
-      if not First then
-         Put_Line (");");
-      end if;
-
-      Put ("end entity ");
-      Put_Name (Get_Name (M));
-      Put_Line (";");
-      New_Line;
-   end Disp_Entity;
-
    procedure Disp_Net_Name (N : Net) is
    begin
       if N = No_Net then
@@ -752,6 +706,56 @@ package body Netlists.Disp_Vhdl is
       New_Line;
    end Disp_Architecture;
 
+   procedure Disp_Entity_Ports (M : Module)
+   is
+      First : Boolean;
+   begin
+      First := True;
+      for P of Ports_Desc (M) loop
+         if First then
+            Put_Line ("  port (");
+            First := False;
+         else
+            Put_Line (";");
+         end if;
+         Put ("    ");
+         Put_Name (P.Name);
+         Put (" : ");
+         case P.Dir is
+            when Port_In =>
+               Put ("in");
+            when Port_Out =>
+               Put ("out");
+            when Port_Inout =>
+               Put ("inout");
+         end case;
+         Put (' ');
+         Put_Type (P.W);
+      end loop;
+      if not First then
+         Put_Line (");");
+      end if;
+   end Disp_Entity_Ports;
+
+   procedure Disp_Entity (M : Module) is
+   begin
+      --  Module id and name.
+      Put_Line ("library ieee;");
+      Put_Line ("use ieee.std_logic_1164.all;");
+      Put_Line ("use ieee.numeric_std.all;");
+      New_Line;
+      Put ("entity ");
+      Put_Name (Get_Name (M));
+      Put_Line (" is");
+
+      Disp_Entity_Ports (M);
+
+      Put ("end entity ");
+      Put_Name (Get_Name (M));
+      Put_Line (";");
+      New_Line;
+   end Disp_Entity;
+
    procedure Disp_Vhdl (M : Module; Is_Top : Boolean) is
    begin
       --  Disp in reverse order.
diff --git a/src/synth/netlists-disp_vhdl.ads b/src/synth/netlists-disp_vhdl.ads
index 62810d0dc..995b15334 100644
--- a/src/synth/netlists-disp_vhdl.ads
+++ b/src/synth/netlists-disp_vhdl.ads
@@ -20,4 +20,7 @@
 
 package Netlists.Disp_Vhdl is
    procedure Disp_Vhdl (M : Module);
+
+   --  Display only the ports (as vhdl) of M.
+   procedure Disp_Entity_Ports (M : Module);
 end Netlists.Disp_Vhdl;