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authorTristan Gingold <tgingold@free.fr>2018-12-15 07:41:09 +0100
committerTristan Gingold <tgingold@free.fr>2018-12-16 07:05:32 +0100
commit814d63034a45f14c6eb1d00d7446537777ed855f (patch)
treeec0a9af9eab6b8785e7b9e96e24c0bbe0899ee4b
parent6f3f9645ef7f05150dd13488025d419deb29c6da (diff)
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Tests for errors in imported units.
-rw-r--r--testsuite/gna/bug094/enta.vhdl20
-rw-r--r--testsuite/gna/bug094/entb.vhdl16
-rw-r--r--testsuite/gna/bug094/pkga_v1.vhdl4
-rw-r--r--testsuite/gna/bug094/pkga_v2.vhdl4
-rw-r--r--testsuite/gna/bug094/pkgb.vhdl3
-rwxr-xr-xtestsuite/gna/bug094/testsuite.sh28
-rw-r--r--testsuite/gna/bug094/topa.vhdl33
-rw-r--r--testsuite/gna/bug094/topb.vhdl33
8 files changed, 141 insertions, 0 deletions
diff --git a/testsuite/gna/bug094/enta.vhdl b/testsuite/gna/bug094/enta.vhdl
new file mode 100644
index 000000000..7c41e5482
--- /dev/null
+++ b/testsuite/gna/bug094/enta.vhdl
@@ -0,0 +1,20 @@
+use work.pkga.all;
+
+entity enta is
+ port (clk : bit;
+ data : word);
+end enta;
+
+architecture behav of enta is
+begin
+ process (clk)
+ variable prev : word;
+ begin
+ if clk = '1' then
+ if prev /= data then
+ report "data has changed" severity note;
+ prev := data;
+ end if;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/bug094/entb.vhdl b/testsuite/gna/bug094/entb.vhdl
new file mode 100644
index 000000000..5dc2a4bde
--- /dev/null
+++ b/testsuite/gna/bug094/entb.vhdl
@@ -0,0 +1,16 @@
+use work.pkgb.all;
+
+entity entb is
+ port (clk : bit;
+ val : natural);
+end entb;
+
+architecture behav of entb is
+begin
+ process (clk)
+ begin
+ if clk = '1' then
+ v := val;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/bug094/pkga_v1.vhdl b/testsuite/gna/bug094/pkga_v1.vhdl
new file mode 100644
index 000000000..23bd2bd98
--- /dev/null
+++ b/testsuite/gna/bug094/pkga_v1.vhdl
@@ -0,0 +1,4 @@
+package pkga is
+ subtype word is bit_vector (31 downto 0);
+end pkga;
+
diff --git a/testsuite/gna/bug094/pkga_v2.vhdl b/testsuite/gna/bug094/pkga_v2.vhdl
new file mode 100644
index 000000000..dd0532939
--- /dev/null
+++ b/testsuite/gna/bug094/pkga_v2.vhdl
@@ -0,0 +1,4 @@
+package pkga is
+ subtype word is bit_vector (0 to 31);
+end pkga;
+
diff --git a/testsuite/gna/bug094/pkgb.vhdl b/testsuite/gna/bug094/pkgb.vhdl
new file mode 100644
index 000000000..a6af85eb1
--- /dev/null
+++ b/testsuite/gna/bug094/pkgb.vhdl
@@ -0,0 +1,3 @@
+package pkgb is
+ shared variable v : natural;
+end pkgb;
diff --git a/testsuite/gna/bug094/testsuite.sh b/testsuite/gna/bug094/testsuite.sh
new file mode 100755
index 000000000..3a37babae
--- /dev/null
+++ b/testsuite/gna/bug094/testsuite.sh
@@ -0,0 +1,28 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+cp pkga_v1.vhdl pkga.vhdl
+analyze pkga.vhdl
+analyze enta.vhdl
+analyze topa.vhdl
+elab_simulate topa
+
+cp pkga_v2.vhdl pkga.vhdl
+analyze_failure topa.vhdl
+
+clean
+rm -f pkga.vhdl
+
+export GHDL_STD_FLAGS="--std=08 -frelaxed-rules"
+analyze pkgb.vhdl
+analyze entb.vhdl
+analyze topb.vhdl
+elab_simulate topb
+
+export GHDL_STD_FLAGS="--std=08"
+analyze_failure topb.vhdl
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/bug094/topa.vhdl b/testsuite/gna/bug094/topa.vhdl
new file mode 100644
index 000000000..fc94dfde4
--- /dev/null
+++ b/testsuite/gna/bug094/topa.vhdl
@@ -0,0 +1,33 @@
+entity topa is
+end topa;
+
+architecture behav of topa is
+ signal clk : bit;
+ signal v : bit_vector (31 downto 0);
+ signal done : boolean := false;
+begin
+ dut : entity work.enta
+ port map (clk => clk,
+ data => v);
+
+ process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ if done then
+ wait;
+ end if;
+ end process;
+
+ process
+ begin
+ v <= x"12345678";
+ wait for 40 ns;
+ v <= x"00000000";
+ wait for 80 ns;
+ done <= true;
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/gna/bug094/topb.vhdl b/testsuite/gna/bug094/topb.vhdl
new file mode 100644
index 000000000..13c5d01c0
--- /dev/null
+++ b/testsuite/gna/bug094/topb.vhdl
@@ -0,0 +1,33 @@
+entity topb is
+end topb;
+
+architecture behav of topb is
+ signal clk : bit;
+ signal v : natural;
+ signal done : boolean := false;
+begin
+ dut : entity work.entb
+ port map (clk => clk,
+ val => v);
+
+ process
+ begin
+ clk <= '0';
+ wait for 10 ns;
+ clk <= '1';
+ wait for 10 ns;
+ if done then
+ wait;
+ end if;
+ end process;
+
+ process
+ begin
+ v <= 2;
+ wait for 40 ns;
+ v <= 4;
+ wait for 80 ns;
+ done <= true;
+ wait;
+ end process;
+end behav;