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author | Tristan Gingold <tgingold@free.fr> | 2019-10-09 18:51:23 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-09 18:51:31 +0200 |
commit | 7bb502c9372456aec9593b043e1fcf96b2e2138a (patch) | |
tree | 5e86ff0f9450f479df44e3f0b8673d9656abdec4 | |
parent | 9b18abcd0ffe810d15d7a36462614b4ae0218a45 (diff) | |
download | ghdl-7bb502c9372456aec9593b043e1fcf96b2e2138a.tar.gz ghdl-7bb502c9372456aec9593b043e1fcf96b2e2138a.tar.bz2 ghdl-7bb502c9372456aec9593b043e1fcf96b2e2138a.zip |
testsuite/synth: add a test for aggregate to net.
-rw-r--r-- | testsuite/synth/lit01/aggr02.vhdl | 39 | ||||
-rw-r--r-- | testsuite/synth/lit01/tb_aggr02.vhdl | 30 | ||||
-rwxr-xr-x | testsuite/synth/lit01/testsuite.sh | 16 |
3 files changed, 85 insertions, 0 deletions
diff --git a/testsuite/synth/lit01/aggr02.vhdl b/testsuite/synth/lit01/aggr02.vhdl new file mode 100644 index 000000000..7920fe818 --- /dev/null +++ b/testsuite/synth/lit01/aggr02.vhdl @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity aggr02 is + port (i0 : natural range 0 to 5; + o : out std_logic_vector (7 downto 0)); +end; + +architecture behav of aggr02 is + type my_enum5 is (e0, e1, e2, e3, e4); + type my_rec is record + en : my_enum5; + cnt : std_logic_vector (3 downto 0); + b : boolean; + c : character; + end record; + + type rec_arr is array (0 to 5) of my_rec; + constant aggr : rec_arr := + (0 => (e0, x"0", false, '0'), + 1 => (e1, x"1", false, '1'), + 2 => (e2, x"2", false, '2'), + 3 => (e3, x"3", false, '3'), + 4 => (e4, x"4", false, '4'), + 5 => (e3, x"5", true, '5')); +begin + process (i0) + variable v : my_rec; + variable r : my_enum5; + begin + v := aggr (i0); + o(3 downto 0) <= v.cnt; + r := e1; + o(7 downto 4) <= x"0"; + if v.en = r then + o (7) <= '1'; + end if; + end process; +end behav; diff --git a/testsuite/synth/lit01/tb_aggr02.vhdl b/testsuite/synth/lit01/tb_aggr02.vhdl new file mode 100644 index 000000000..d864557ad --- /dev/null +++ b/testsuite/synth/lit01/tb_aggr02.vhdl @@ -0,0 +1,30 @@ +entity tb_aggr02 is +end tb_aggr02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_aggr02 is + signal i0 : natural range 0 to 5; + signal o : std_logic_vector(7 downto 0); +begin + dut: entity work.aggr02 + port map (i0, o); + + process + begin + i0 <= 0; + wait for 1 ns; + assert o = x"00" severity failure; + + i0 <= 1; + wait for 1 ns; + assert o = x"81" severity failure; + + i0 <= 2; + wait for 1 ns; + assert o = x"02" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/lit01/testsuite.sh b/testsuite/synth/lit01/testsuite.sh new file mode 100755 index 000000000..a273b86fc --- /dev/null +++ b/testsuite/synth/lit01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in aggr02; do + analyze $t.vhdl tb_$t.vhdl + elab_simulate tb_$t + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_$t.vhdl + elab_simulate tb_$t --ieee-asserts=disable-at-0 + clean +done + +echo "Test successful" |