testsuite/gna: add a test for #1820

4 files changed, 161 insertions, 0 deletions

diff --git a/testsuite/gna/issue1820/cordic.vhdl b/testsuite/gna/issue1820/cordic.vhdl
new file mode 100644
index 000000000..dc48d19de
--- /dev/null
+++ b/testsuite/gna/issue1820/cordic.vhdl
@@ -0,0 +1,64 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.math_real.all;
+
+entity cordic is
+	generic (
+		SIZE: natural := 16
+	);
+	port (
+		vec: in std_logic;
+		x_i: in std_logic_vector(SIZE-1 downto 0);
+		y_i: in std_logic_vector(SIZE-1 downto 0);
+		z_i: in std_logic_vector(SIZE-1 downto 0);
+		x_o: out std_logic_vector(SIZE-1 downto 0);
+		y_o: out std_logic_vector(SIZE-1 downto 0);
+		z_o: out std_logic_vector(SIZE-1 downto 0)
+	) ;
+end entity ; -- cordic
+
+architecture desenrollado of cordic is
+
+	type matriz is array(natural range <>) of std_logic_vector(SIZE-1 downto 0);
+	signal x, y, z: matriz(0 to SIZE);
+	signal a: std_logic := '1';
+
+	--type matriz_atan is array (0 to SIZE-1) of std_logic_vector(SIZE-1 downto 0);
+	--constant atan: matriz_atan := (
+	--	for i in 0 to SIZE-1 loop
+	--		std_logic_vector(),
+	--	end loop ; 
+	--)
+	signal PRUEBA: std_logic_vector(SIZE-1 downto 0) := std_logic_vector(to_unsigned(integer(0.25*2**SIZE+0.5), SIZE));
+	constant HOLA: real := 0.5;
+
+begin
+
+	x(0) <= x_i;
+	y(0) <= y_i;
+	z(0) <= z_i;
+
+	x_o <= x(SIZE);
+	y_o <= y(SIZE);
+	z_o <= z(SIZE);
+
+	etapas : for i in 0 to SIZE-1 generate
+		etapa: entity work.etapa
+			generic map(
+				SIZE => SIZE,
+				STEP => i
+			)
+			port map(
+				vec => vec,
+				x_i => x(i),
+				y_i => y(i),
+				z_i => z(i),
+				atan_i => (others => '0'),
+				x_o => x(i+1),
+				y_o => y(i+1),
+				z_o => z(i+1)
+			);
+	end generate ; -- etapas
+
+end architecture ; -- desenrollado
diff --git a/testsuite/gna/issue1820/desenrollado_tb.vhdl b/testsuite/gna/issue1820/desenrollado_tb.vhdl
new file mode 100644
index 000000000..dad34dd51
--- /dev/null
+++ b/testsuite/gna/issue1820/desenrollado_tb.vhdl
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity desenrollado_tb is
+end entity ; -- desenrollado_tb
+
+architecture desenrollado_tb_arq of desenrollado_tb is
+
+	constant SIZE: natural := 16;
+
+	signal vec_tb: std_logic;
+	signal x_i_tb: std_logic_vector(SIZE-1 downto 0);
+	signal y_i_tb: std_logic_vector(SIZE-1 downto 0);
+	signal z_i_tb: std_logic_vector(SIZE-1 downto 0);
+	signal x_o_tb: std_logic_vector(SIZE-1 downto 0);
+	signal y_o_tb: std_logic_vector(SIZE-1 downto 0);
+	signal z_o_tb: std_logic_vector(SIZE-1 downto 0);
+
+begin
+
+	vec_tb <= '1', '0' after 600 ns;
+	x_i_tb <= (4 => '0', others => '1');
+	y_i_tb <= (4 => '0', others => '1');
+	z_i_tb <= (4 => '0', others => '1');
+
+	cordic: entity work.cordic(desenrollado)
+		port map(
+			vec => vec_tb,
+			x_i => x_i_tb,
+			y_i => y_i_tb,
+			z_i => z_i_tb,
+			x_o => x_o_tb,
+			y_o => y_o_tb,
+			z_o => z_o_tb
+		) ;
+end architecture ; -- desenrollado_tb_arq
diff --git a/testsuite/gna/issue1820/etapa.vhdl b/testsuite/gna/issue1820/etapa.vhdl
new file mode 100644
index 000000000..82b0baaec
--- /dev/null
+++ b/testsuite/gna/issue1820/etapa.vhdl
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity etapa is
+	generic (
+		SIZE: natural := 16;
+		STEP: natural := 1
+	);
+	port (
+		vec: in std_logic;
+		x_i: in std_logic_vector(SIZE-1 downto 0);
+		y_i: in std_logic_vector(SIZE-1 downto 0);
+		z_i: in std_logic_vector(SIZE-1 downto 0);
+		atan_i: in std_logic_vector(SIZE-1 downto 0);
+		x_o: out std_logic_vector(SIZE-1 downto 0);
+		y_o: out std_logic_vector(SIZE-1 downto 0);
+		z_o: out std_logic_vector(SIZE-1 downto 0)
+	) ;
+end entity ; -- etapa
+
+architecture etapa_arq of etapa is
+
+	signal d_i: std_logic;
+	signal d_i_slv: std_logic_vector(SIZE-1 downto 0);
+	signal d_i_n_slv: std_logic_vector(SIZE-1 downto 0);
+
+	signal x_shifted: std_logic_vector(SIZE-1 downto 0);
+	signal y_shifted: std_logic_vector(SIZE-1 downto 0);
+	signal c_x_shifted: std_logic_vector(SIZE-1 downto 0);
+	signal c_y_shifted: std_logic_vector(SIZE-1 downto 0);
+	signal c_z_i: std_logic_vector(SIZE-1 downto 0);
+
+begin
+
+	d_i <= y_i(SIZE-1) when vec = '1' else z_i(SIZE-1);
+	d_i_slv <= (SIZE-2 downto 0 => '0') & d_i;
+	d_i_n_slv <= (SIZE-2 downto 0 => '0') & not(d_i);
+
+	x_shifted <= std_logic_vector(shift_right(signed(x_i), STEP));
+	y_shifted <= std_logic_vector(shift_right(signed(y_i), STEP));
+
+	c_x_shifted <= x_shifted xor (0 to SIZE-1 => d_i);
+	c_y_shifted <= y_shifted xor (0 to SIZE-1 => not(d_i));
+	c_z_i <= atan_i xor (0 to SIZE-1 => not(d_i));
+
+	x_o <= std_logic_vector(signed(x_i) + signed(c_y_shifted) + signed(d_i_n_slv));
+	y_o <= std_logic_vector(signed(y_i) + signed(c_x_shifted) + signed(d_i_slv));
+	z_o <= std_logic_vector(signed(z_i) + signed(c_z_i) + signed(d_i_n_slv));
+
+end architecture ; -- etapa_arq
diff --git a/testsuite/gna/issue1820/testsuite.sh b/testsuite/gna/issue1820/testsuite.sh
new file mode 100755
index 000000000..8e0611275
--- /dev/null
+++ b/testsuite/gna/issue1820/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze etapa.vhdl cordic.vhdl desenrollado_tb.vhdl 
+analyze cordic.vhdl desenrollado_tb.vhdl etapa.vhdl 
+
+clean
+
+echo "Test successful"