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| author | Tristan Gingold <tgingold@free.fr> | 2014-01-05 17:09:57 +0100 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-01-05 17:09:57 +0100 | 
| commit | 6db77714c4d66adfb58872d05c8e3aaef55c7e00 (patch) | |
| tree | cdf847208b82a3f4e8143f9931063a24aff885db | |
| parent | 6ab63305d08ac83573aeb65bfd4dd266b8ad9aed (diff) | |
| download | ghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.tar.gz ghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.tar.bz2 ghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.zip | |
Fix bug17759: individual associated to an element of array of array.
| -rw-r--r-- | sem_assocs.adb | 1 | ||||
| -rw-r--r-- | testsuite/gna/bug17759/test.vhdl | 43 | ||||
| -rwxr-xr-x | testsuite/gna/bug17759/testsuite.sh | 10 | 
3 files changed, 54 insertions, 0 deletions
| diff --git a/sem_assocs.adb b/sem_assocs.adb index 87081f4cf..c4a9bce74 100644 --- a/sem_assocs.adb +++ b/sem_assocs.adb @@ -489,6 +489,7 @@ package body Sem_Assocs is                 Sub := Create_Iir (Iir_Kind_Association_Element_By_Individual);                 Location_Copy (Sub, Formal);                 Set_Formal (Sub, Iassoc); +               Set_Associated (Iassoc, Sub);                 Iassoc := Sub;              else                 case Get_Kind (Sub) is diff --git a/testsuite/gna/bug17759/test.vhdl b/testsuite/gna/bug17759/test.vhdl new file mode 100644 index 000000000..8f019b355 --- /dev/null +++ b/testsuite/gna/bug17759/test.vhdl @@ -0,0 +1,43 @@ + +library ieee; +use ieee.std_logic_1164.all; + +package test is +  type array_t is array (1 downto 0) of std_logic_vector(1 downto 0); +end package test; + + +use work.test.all; +library ieee; +use ieee.std_logic_1164.all; + +entity b is +  port (io_a : inout array_t); +end entity b; + +architecture rtl of b is +begin  -- architecture dummy +  io_a <= ("HH", "LL"); +end architecture rtl; + + +use work.test.all; +library ieee; +use ieee.std_logic_1164.all; + +entity a is +    port (io_v : inout std_logic_vector(1 downto 0); +          io_1 : inout std_logic; +          io_2 : inout std_logic); +end entity a; + +architecture rtl of a is +  component b is +    port (io_a : inout array_t); +  end component b; +begin  -- architecture rtl +  b1 : b port map ( +    io_a(0) => io_v, +    io_a(1)(0) => io_1, +    io_a(1)(1) => io_2); +end architecture rtl; diff --git a/testsuite/gna/bug17759/testsuite.sh b/testsuite/gna/bug17759/testsuite.sh new file mode 100755 index 000000000..3de908b5c --- /dev/null +++ b/testsuite/gna/bug17759/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze test.vhdl +elab_simulate a + +clean + +echo "Test successful" | 
