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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-04 08:56:44 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-04 08:56:44 +0200 |
| commit | 6d8dbed5efcbbabbc886beb9a0291e43013010bc (patch) | |
| tree | f8b903eacf8bc7d1fc16eb0262587c7dbcddc60a | |
| parent | 4ce5f0c046685ad630f9eb6140e87a66be020f94 (diff) | |
| download | ghdl-6d8dbed5efcbbabbc886beb9a0291e43013010bc.tar.gz ghdl-6d8dbed5efcbbabbc886beb9a0291e43013010bc.tar.bz2 ghdl-6d8dbed5efcbbabbc886beb9a0291e43013010bc.zip | |
testsuite/synth: add a test for #2159
| -rw-r--r-- | testsuite/synth/issue2159/bug.vhdl | 21 | ||||
| -rwxr-xr-x | testsuite/synth/issue2159/testsuite.sh | 8 |
2 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/issue2159/bug.vhdl b/testsuite/synth/issue2159/bug.vhdl new file mode 100644 index 000000000..0dfd4a2fb --- /dev/null +++ b/testsuite/synth/issue2159/bug.vhdl @@ -0,0 +1,21 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + generic ( + LEN_DATA : positive := 32; + MAX_STEP : positive := 8 + ); + port ( + src : in std_ulogic_vector(LEN_DATA-1 downto 0); + dst : out std_ulogic_vector(LEN_DATA-1 downto 0); + + step : in integer range 0 to MAX_STEP-1 + ); +end bug; + +architecture rtl of bug is + constant STEP_SIZE : positive := 2; +begin + dst <= src ror step*STEP_SIZE; +end architecture; diff --git a/testsuite/synth/issue2159/testsuite.sh b/testsuite/synth/issue2159/testsuite.sh new file mode 100755 index 000000000..567d44382 --- /dev/null +++ b/testsuite/synth/issue2159/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +synth_only bug + +echo "Test successful" |