Handle shared variables.

4 files changed, 59 insertions, 3 deletions

diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index 953fddc41..c8777f722 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -39,6 +39,7 @@ from pyVHDLModel.VHDLModel import (
     Constant as VHDLModel_Constant,
     DeferredConstant as VHDLModel_DeferredConstant,
     Variable as VHDLModel_Variable,
+    SharedVariable as VHDLModel_SharedVariable,
     Signal as VHDLModel_Signal,
     Expression,
     SubTypeOrSymbol,
@@ -106,6 +107,22 @@ class Variable(VHDLModel_Variable):
 
 
 @export
+class SharedVariable(VHDLModel_SharedVariable):
+    def __init__(self, name: str, subType: SubTypeOrSymbol):
+        super().__init__(name)
+
+        self._name = name
+        self._subType = subType
+
+    @classmethod
+    def parse(cls, node):
+        name = GetNameOfNode(node)
+        subTypeIndication = GetSubtypeIndicationFromNode(node, "variable", name)
+
+        return cls(name, subTypeIndication)
+
+
+@export
 class Signal(VHDLModel_Signal):
     def __init__(
         self, name: str, subType: SubTypeOrSymbol, defaultExpression: Expression
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 2b2a44e60..18b4160b8 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -366,6 +366,14 @@ def GetDeclaredItemsFromChainedNodes(nodeChain: Iir, entity: str, name: str):
             from pyGHDL.dom.Object import Constant
 
             result.append(Constant.parse(item))
+
+        elif kind == nodes.Iir_Kind.Variable_Declaration:
+            from pyGHDL.dom.Object import SharedVariable
+
+            if nodes.Get_Shared_Flag(item):
+                result.append(SharedVariable.parse(item))
+            else:
+                raise DOMException("Found non-shared variable.")
         elif kind == nodes.Iir_Kind.Signal_Declaration:
             from pyGHDL.dom.Object import Signal
 
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 0509b826d..c4f76acaa 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -24,7 +24,7 @@ from pyGHDL.dom.DesignUnit import (
     Context,
     Component,
 )
-from pyGHDL.dom.Object import Constant, Signal
+from pyGHDL.dom.Object import Constant, Signal, SharedVariable
 from pyGHDL.dom.InterfaceItem import (
     GenericConstantInterfaceItem,
     PortSignalInterfaceItem,
@@ -302,6 +302,16 @@ class PrettyPrint:
                     expr=str(item.DefaultExpression),
                 )
             )
+        elif isinstance(item, SharedVariable):
+            buffer.append(
+                "{prefix}- shared variable {name} : {subtype}".format(
+                    prefix=prefix,
+                    name=item.Name,
+                    subtype=self.formatSubtypeIndication(
+                        item.SubType, "shared variable", item.Name
+                    ),
+                )
+            )
         elif isinstance(item, Signal):
             buffer.append(
                 "{prefix}- signal {name} : {subtype}{initValue}".format(
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl
index 8653cb088..72af911eb 100644
--- a/testsuite/pyunit/Current.vhdl
+++ b/testsuite/pyunit/Current.vhdl
@@ -20,16 +20,31 @@ end entity entity_1;
 
 architecture behav of entity_1 is
 	constant MAX : positive := -25;
-	signal rst : std_logic := foo'('U');
+	signal rst : std_logic := foo('U');
 
 	type newInt is range -4 to 3;
+	type arr is array(natural range <>) of integer;
+	type rec is record
+		elem1 : bit;
+		elem2 : boolean;
+	end record;
+	type enum is (e1, e2, e3);
 	subtype uint8 is integer range 0 to 255;
 
-	function foo(a : integer; b : boolean) return bit is
+--	file f : text;
+
+	function foo generic(g : int8) (a : integer; b : boolean) return bit is
 	begin
 
 	end function;
 
+  shared variable foo : bob;
+
+	procedure proc(spam : egg) is
+	begin
+
+	end procedure;
+
 	alias bar is boolean;
 begin
 	process(Clock)
@@ -46,6 +61,12 @@ end architecture behav;
 
 package package_1 is
 	constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3;
+
+	component comp is
+		port (
+			clk : std
+		);
+	end component;
 end package;
 
 package body package_1 is