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| author | Tristan Gingold <tgingold@free.fr> | 2021-07-01 06:18:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-07-01 06:18:57 +0200 |
| commit | 69e6630acb723282ddde95ad0681ac71686df8e8 (patch) | |
| tree | 0b7e3d3ec3fc2f97e189df2b2e6b2fe112bba8fc | |
| parent | 523ef899957ede0507964116d93c98f92cfc97ea (diff) | |
| download | ghdl-69e6630acb723282ddde95ad0681ac71686df8e8.tar.gz ghdl-69e6630acb723282ddde95ad0681ac71686df8e8.tar.bz2 ghdl-69e6630acb723282ddde95ad0681ac71686df8e8.zip | |
adjust previous commit (no identifier in Psl_Default_Clock)
| -rw-r--r-- | pyGHDL/libghdl/vhdl/nodes.py | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes_walk.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_specs.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-utils.adb | 1 |
5 files changed, 5 insertions, 4 deletions
diff --git a/pyGHDL/libghdl/vhdl/nodes.py b/pyGHDL/libghdl/vhdl/nodes.py index a7ee2e037..923f49606 100644 --- a/pyGHDL/libghdl/vhdl/nodes.py +++ b/pyGHDL/libghdl/vhdl/nodes.py @@ -978,7 +978,6 @@ class Iir_Kinds: Iir_Kind.Case_Generate_Statement, Iir_Kind.For_Generate_Statement, Iir_Kind.Component_Instantiation_Statement, - Iir_Kind.Psl_Default_Clock, ] Simple_Concurrent_Statement = [ diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 71ede45f0..9ba5a43fa 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6875,8 +6875,7 @@ package Vhdl.Nodes is --Iir_Kind_If_Generate_Statement --Iir_Kind_Case_Generate_Statement --Iir_Kind_For_Generate_Statement - --Iir_Kind_Component_Instantiation_Statement - Iir_Kind_Psl_Default_Clock; + Iir_Kind_Component_Instantiation_Statement; subtype Iir_Kinds_Simple_Concurrent_Statement is Iir_Kind range Iir_Kind_Sensitized_Process_Statement .. diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index 0f9b0e8ab..8a39a1bd1 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -156,7 +156,7 @@ package body Vhdl.Nodes_Walk is begin El := Chain; while Is_Valid (El) loop - case Iir_Kinds_Concurrent_Statement (Get_Kind (El)) is + case Get_Kind (El) is when Iir_Kinds_Simple_Concurrent_Statement | Iir_Kind_Component_Instantiation_Statement | Iir_Kind_Psl_Default_Clock => diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 456b0b055..b81058280 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -513,6 +513,8 @@ package body Vhdl.Sem_Specs is null; when Iir_Kind_Anonymous_Type_Declaration => null; + when Iir_Kind_Psl_Default_Clock => + null; when others => Error_Kind ("sem_named_entity", Ent); end case; diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb index d90bef487..2a60e82e7 100644 --- a/src/vhdl/vhdl-utils.adb +++ b/src/vhdl/vhdl-utils.adb @@ -362,6 +362,7 @@ package body Vhdl.Utils is | Iir_Kind_Nature_Element_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Declaration + | Iir_Kind_Psl_Default_Clock | Iir_Kind_Package_Pathname | Iir_Kind_Absolute_Pathname | Iir_Kind_Relative_Pathname |