synth: add ule, fix gate number.

3 files changed, 41 insertions, 30 deletions

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 14323413b..20626b2c3 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -353,6 +353,8 @@ package body Netlists.Builders is
 
       Create_Compare_Module (Design, Res.M_Compare (Id_Ult),
                              Get_Identifier ("ult"), Id_Ult);
+      Create_Compare_Module (Design, Res.M_Compare (Id_Ule),
+                             Get_Identifier ("ule"), Id_Ule);
 
       Create_Concat_Modules (Res);
       Create_Const_Modules (Res);
@@ -403,6 +405,7 @@ package body Netlists.Builders is
       Wd : constant Width := Get_Width (L);
       pragma Assert (Wd /= No_Width);
       pragma Assert (Get_Width (R) = Wd);
+      pragma Assert (Ctxt.M_Dyadic (Id) /= No_Module);
       Inst : Instance;
       O : Net;
    begin
@@ -418,6 +421,7 @@ package body Netlists.Builders is
                            Id : Monadic_Module_Id;
                            Op : Net) return Net
    is
+      pragma Assert (Ctxt.M_Monadic (Id) /= No_Module);
       Inst : Instance;
       O : Net;
    begin
@@ -435,6 +439,7 @@ package body Netlists.Builders is
       Wd : constant Width := Get_Width (L);
       pragma Assert (Wd /= No_Width);
       pragma Assert (Get_Width (R) = Wd);
+      pragma Assert (Ctxt.M_Compare (Id) /= No_Module);
       Inst : Instance;
       O : Net;
    begin
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index df40831bf..0f7418167 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -203,7 +203,7 @@ package body Netlists.Disp_Vhdl is
             Port_Name := Get_Output_Desc (Get_Module (Inst), Idx).Name;
             case Get_Sname_Kind (Inst_Name) is
                when Sname_Version =>
-                  Put ("net_");
+                  Put ("n");
                   Put_Name_Version (Inst_Name);
                   Put ("_");
                   Put_Interface_Name (Port_Name);
@@ -497,8 +497,14 @@ package body Netlists.Disp_Vhdl is
          when Id_Ult =>
             Disp_Template ("  \o0 <= '1' when \ui0 < \ui1 else '0';" & NL,
                            Inst);
+         when Id_Ule =>
+            Disp_Template ("  \o0 <= '1' when \ui0 <= \ui1 else '0';" & NL,
+                           Inst);
          when Id_Eq =>
             Disp_Template ("  \o0 <= '1' when \i0 = \i1 else '0';" & NL, Inst);
+         when Id_Ne =>
+            Disp_Template ("  \o0 <= '1' when \i0 /= \i1 else '0';" & NL,
+                           Inst);
          when Id_Or =>
             Disp_Template ("  \o0 <= \i0 or \i1;" & NL, Inst);
          when Id_And =>
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 90615dc7a..60955221c 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -44,39 +44,39 @@ package Netlists.Gates is
    Id_Ne  : constant Module_Id := 17;
    Id_Ule : constant Module_Id := 18;
    Id_Sle : constant Module_Id := 19;
-   Id_Ult : constant Module_Id := 18;
-   Id_Slt : constant Module_Id := 19;
-   Id_Uge : constant Module_Id := 18;
-   Id_Sge : constant Module_Id := 19;
-   Id_Ugt : constant Module_Id := 18;
-   Id_Sgt : constant Module_Id := 19;
+   Id_Ult : constant Module_Id := 20;
+   Id_Slt : constant Module_Id := 21;
+   Id_Uge : constant Module_Id := 22;
+   Id_Sge : constant Module_Id := 23;
+   Id_Ugt : constant Module_Id := 24;
+   Id_Sgt : constant Module_Id := 25;
 
    subtype Compare_Module_Id is Module_Id range Id_Eq .. Id_Sgt;
 
-   Id_Red_And : constant Module_Id := 20;
-   Id_Red_Or  : constant Module_Id := 21;
+   Id_Red_And : constant Module_Id := 26;
+   Id_Red_Or  : constant Module_Id := 27;
 
-   Id_Concat2 : constant Module_Id := 22;
-   Id_Concat3 : constant Module_Id := 23;
-   Id_Concat4 : constant Module_Id := 24;
+   Id_Concat2 : constant Module_Id := 28;
+   Id_Concat3 : constant Module_Id := 29;
+   Id_Concat4 : constant Module_Id := 30;
 
    subtype Concat_Module_Id is Module_Id range Id_Concat2 .. Id_Concat4;
 
-   Id_Split2 : constant Module_Id := 25;
-   Id_Split3 : constant Module_Id := 26;
+   Id_Split2 : constant Module_Id := 31;
+   Id_Split3 : constant Module_Id := 32;
 
    --  Inputs: s, i0, i1
    --  Output: o
-   Id_Mux2 : constant Module_Id := 27;
+   Id_Mux2 : constant Module_Id := 33;
    --  Inputs: s, i0, i1, s2, s3
    --  Output: o
-   Id_Mux4 : constant Module_Id := 28;
+   Id_Mux4 : constant Module_Id := 34;
 
    --  Like a wire: the output is equal to the input, but could be elimited
    --  at any time.  Isignal has an initial value.
-   Id_Signal  : constant Module_Id := 29;
-   Id_Isignal : constant Module_Id := 30;
-   Id_Output  : constant Module_Id := 31;
+   Id_Signal  : constant Module_Id := 35;
+   Id_Isignal : constant Module_Id := 36;
+   Id_Output  : constant Module_Id := 37;
 
    --  Note: initial values must be constant nets.
    --
@@ -85,44 +85,44 @@ package Netlists.Gates is
    --  input.
    --  Inputs: CLK, D
    --  Output: Q
-   Id_Dff   : constant Module_Id := 32;
+   Id_Dff   : constant Module_Id := 38;
 
    --  A DFF with an asynchronous reset.  Note that the asynchronous reset
    --  has priority over the clock.  When RST is asserted, the value is
    --  set to RST_VAL.
    --  Inputs: CLK, D, RST, RST_VAL
    --  Output: Q
-   Id_Adff  : constant Module_Id := 33;
+   Id_Adff  : constant Module_Id := 39;
 
    --  A simple DFF with an initial value (must be constant).  This is
    --  for FPGAs.
-   Id_Idff  : constant Module_Id := 34;
+   Id_Idff  : constant Module_Id := 40;
    --  A DFF with an asynchronous reset and an initial value.
-   Id_Iadff : constant Module_Id := 35;
+   Id_Iadff : constant Module_Id := 41;
 
    --  Width change: truncate or extend.  Sign is know in order to possibly
    --  detect loss of value.
-   Id_Utrunc : constant Module_Id := 40;
-   Id_Strunc : constant Module_Id := 41;
-   Id_Uextend : constant Module_Id := 42;
-   Id_Sextend : constant Module_Id := 43;
+   Id_Utrunc : constant Module_Id := 42;
+   Id_Strunc : constant Module_Id := 43;
+   Id_Uextend : constant Module_Id := 44;
+   Id_Sextend : constant Module_Id := 45;
 
    subtype Truncate_Module_Id is Module_Id range Id_Utrunc .. Id_Strunc;
    subtype Extend_Module_Id is Module_Id range Id_Uextend .. Id_Sextend;
 
    --  Extract a bit or a slice at a constant offset.
    --  OUT := IN0[OFF+WD-1:OFF]
-   Id_Extract : constant Module_Id := 44;
+   Id_Extract : constant Module_Id := 46;
 
    --  OUT := IN0[IN1*STEP+OFF+WD-1:IN1*STEP+OFF]
-   Id_Dyn_Extract : constant Module_Id := 45;
+   Id_Dyn_Extract : constant Module_Id := 47;
 
    --  This gate has two inputs A, B and one parameter POS.
    --  It replaces bits POS + width(B) - 1 .. POS of A by B, ie:
    --  T := A;
    --  T (POS + width(B) - 1 .. POS) := B
    --  OUT := T.
-   Id_Insert : constant Module_Id := 47;
+   Id_Insert : constant Module_Id := 48;
 
    --  Positive/rising edge detector.  This is a pseudo gate.
    --  A negative edge detector can be made using by negating the clock before