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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2022-12-22 23:14:54 +0100 |
|---|---|---|
| committer | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2022-12-23 23:44:14 +0100 |
| commit | 5e5e2fb50ed6eba32d614c9c566e280a6f992acb (patch) | |
| tree | cf631c578e0b64c53841ffa8bc2dcb1e78c754a7 | |
| parent | 6cbd112a8685f4439394f21965404dd0d7c41567 (diff) | |
| download | ghdl-5e5e2fb50ed6eba32d614c9c566e280a6f992acb.tar.gz ghdl-5e5e2fb50ed6eba32d614c9c566e280a6f992acb.tar.bz2 ghdl-5e5e2fb50ed6eba32d614c9c566e280a6f992acb.zip | |
Changed doc comment position.
| -rw-r--r-- | testsuite/pyunit/dom/examples/SimpleEntity.vhdl | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl index bdeae47e1..8acc3ddb5 100644 --- a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl +++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl @@ -35,8 +35,10 @@ entity Counter is end entity; --- Synthesizable and simulatable variant of a generic counter. architecture rtl of Counter is + -- Synthesizable and simulatable variant of a generic counter. + + -- Internal counter value signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); begin process (Clock) |