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author | Tristan Gingold <tgingold@free.fr> | 2023-04-20 18:28:41 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-20 18:29:31 +0200 |
commit | 5d31696367928825147750794386e055336f576e (patch) | |
tree | b2c31b9c85c5c87a41a9b819cfb0d36b45a22ec5 | |
parent | b72b92ad29ec7b60a3abd8b344c6bddca0c68ee8 (diff) | |
download | ghdl-5d31696367928825147750794386e055336f576e.tar.gz ghdl-5d31696367928825147750794386e055336f576e.tar.bz2 ghdl-5d31696367928825147750794386e055336f576e.zip |
testsuite/gna: add a test for #2417
-rw-r--r-- | testsuite/gna/issue2417/repro1.vhdl | 53 | ||||
-rw-r--r-- | testsuite/gna/issue2417/repro2.vhdl | 61 | ||||
-rwxr-xr-x | testsuite/gna/issue2417/testsuite.sh | 14 |
3 files changed, 128 insertions, 0 deletions
diff --git a/testsuite/gna/issue2417/repro1.vhdl b/testsuite/gna/issue2417/repro1.vhdl new file mode 100644 index 000000000..5986f80e1 --- /dev/null +++ b/testsuite/gna/issue2417/repro1.vhdl @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; + +package repro1_pkg is + procedure p(signal ack: bit; variable v: inout std_logic_vector); +end repro1_pkg; + +package body repro1_pkg is + procedure p(signal ack: bit; variable v: inout std_logic_vector) is + begin + wait until ack = '1'; + v := not v; + end p; +end; + +library ieee; +use ieee.std_logic_1164.all; +use work.repro1_pkg.all; + +entity repro1 is +end; + +architecture arch of repro1 is + signal ack1, ack2 : bit := '0'; +begin + process + variable v : std_ulogic_vector(7 downto 0); + begin + v := x"c3"; + p (ack1, v); + assert v = x"3c" severity failure; + wait; + end process; + + process + variable v : std_ulogic_vector(7 downto 0); + begin + v := x"e1"; + p (ack2, v); + assert v = x"1e" severity failure; + wait; + end process; + + process + begin + ack1 <= '1'; + wait for 1 ns; + ack2 <= '1'; + wait for 1 ns; + report "end of test"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/repro2.vhdl b/testsuite/gna/issue2417/repro2.vhdl new file mode 100644 index 000000000..917d7505b --- /dev/null +++ b/testsuite/gna/issue2417/repro2.vhdl @@ -0,0 +1,61 @@ +package repro2_pkg is + function resolver(v : bit_vector) return bit; + + subtype sbit_vector is (resolver) bit_vector; + + procedure p(signal ack: bit; variable v: inout sbit_vector); +end repro2_pkg; + +package body repro2_pkg is + function resolver(v : bit_vector) return bit is + begin + if v = (v'range => '0') then + return '0'; + else + return '1'; + end if; + end resolver; + + procedure p(signal ack: bit; variable v: inout sbit_vector) is + begin + wait until ack = '1'; + v := not v; + end p; +end; + +use work.repro2_pkg.all; + +entity repro2 is +end; + +architecture arch of repro2 is + signal ack1, ack2 : bit := '0'; +begin + process + variable v : bit_vector(7 downto 0); + begin + v := x"c3"; + p (ack1, v); + assert v = x"3c" severity failure; + wait; + end process; + + process + variable v : bit_vector(7 downto 0); + begin + v := x"e1"; + p (ack2, v); + assert v = x"1e" severity failure; + wait; + end process; + + process + begin + ack1 <= '1'; + wait for 1 ns; + ack2 <= '1'; + wait for 1 ns; + report "end of test"; + wait; + end process; +end; diff --git a/testsuite/gna/issue2417/testsuite.sh b/testsuite/gna/issue2417/testsuite.sh new file mode 100755 index 000000000..fca1b9b9e --- /dev/null +++ b/testsuite/gna/issue2417/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate repro1 + +analyze repro2.vhdl +elab_simulate repro2 + +clean + +echo "Test successful" |