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authorTristan Gingold <tgingold@free.fr>2022-10-06 20:37:11 +0200
committerTristan Gingold <tgingold@free.fr>2022-10-06 20:37:11 +0200
commit4c4467cd5449ff3d9a337850309199bd380ce5e0 (patch)
treecbeacbfc38132b70ca13dfc5202c622d0dcf3e4e
parent6bb1a59f471b3e91bb4c68567a841c49dd9273ae (diff)
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simul: recompute object alias offsets
-rw-r--r--src/simul/simul-vhdl_elab.adb15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index a8c285be6..89e75e7c7 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -358,15 +358,28 @@ package body Simul.Vhdl_Elab is
Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl));
Gather_Signal ((Mode_Stable, Decl, Inst, null, null, null,
No_Sensitivity_Index, No_Signal_Index,
- T, Pfx));
+ No_Connect_Index, T, Pfx));
end;
when Iir_Kind_Object_Alias_Declaration =>
-- In case it aliases a signal.
declare
+ Marker : Mark_Type;
V : Valtyp;
+ Base : Valtyp;
+ Typ : Type_Acc;
+ Off : Value_Offsets;
begin
V := Get_Value (Inst, Decl);
Convert_Type_Width (V.Typ);
+
+ -- Recompute alias offsets.
+ Mark_Expr_Pool (Marker);
+ Synth.Vhdl_Stmts.Synth_Assignment_Prefix
+ (Inst, Get_Name (Decl), Base, Typ, Off);
+ V.Val.A_Off := Off;
+ pragma Assert (Base.Val = V.Val.A_Obj);
+ pragma Unreferenced (Typ);
+ Release_Expr_Pool (Marker);
end;
when Iir_Kind_Disconnection_Specification =>
Gather_Disconnection (Inst, Decl);