testsuite/synth: add mem2d01 tests.

7 files changed, 327 insertions, 0 deletions

diff --git a/testsuite/synth/mem2d01/dpram1r.vhdl b/testsuite/synth/mem2d01/dpram1r.vhdl
new file mode 100644
index 000000000..2c1335a1b
--- /dev/null
+++ b/testsuite/synth/mem2d01/dpram1r.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram1r is
+  port (raddr : natural range 0 to 3;
+        rbit  : natural range 0 to 7;
+        rdat : out std_logic;
+        waddr : natural range 0 to 3;
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram1r;
+
+architecture behav of dpram1r is
+  type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (raddr)(rbit);
+      mem (waddr) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/dpram2r.vhdl b/testsuite/synth/mem2d01/dpram2r.vhdl
new file mode 100644
index 000000000..4419d5086
--- /dev/null
+++ b/testsuite/synth/mem2d01/dpram2r.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram2r is
+  port (raddr : natural range 0 to 3;
+        rnib  : natural range 0 to 1;
+        rdat : out std_logic_vector (3 downto 0);
+        waddr : natural range 0 to 3;
+        wdat : std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram2r;
+
+architecture behav of dpram2r is
+  type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      rdat <= mem (raddr)(rnib * 4 + 3 downto rnib * 4);
+      mem (waddr) <= wdat;
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/dpram2w.vhdl b/testsuite/synth/mem2d01/dpram2w.vhdl
new file mode 100644
index 000000000..c1b1c83d0
--- /dev/null
+++ b/testsuite/synth/mem2d01/dpram2w.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dpram2w is
+  port (waddr : natural range 0 to 3;
+        wnib  : natural range 0 to 1;
+        wdat : std_logic_vector (3 downto 0);
+        raddr : natural range 0 to 3;
+        rdat : out std_logic_vector (7 downto 0);
+        clk : std_logic);
+end dpram2w;
+
+architecture behav of dpram2w is
+  type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
+  signal mem : memtype;
+begin
+  process (clk)
+  begin
+    if rising_edge (clk) then
+      mem (waddr)(wnib * 4 + 3 downto wnib * 4) <= wdat;
+      rdat <= mem (raddr);
+    end if;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/tb_dpram1r.vhdl b/testsuite/synth/mem2d01/tb_dpram1r.vhdl
new file mode 100644
index 000000000..5cfaa76ba
--- /dev/null
+++ b/testsuite/synth/mem2d01/tb_dpram1r.vhdl
@@ -0,0 +1,72 @@
+entity tb_dpram1r is
+end tb_dpram1r;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram1r is
+  signal raddr : natural range 0 to 3;
+  signal rbit : natural range 0 to 7;
+  signal rdat : std_logic;
+  signal waddr : natural range 0 to 3;
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram1r
+    port map (raddr => raddr, rbit => rbit, rdat => rdat,
+              waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= 0;
+    rbit <= 0;
+    waddr <= 1;
+    wdat <= x"e1";
+    pulse;
+
+    raddr <= 1;
+    rbit <= 0;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = '1' severity failure;
+
+    raddr <= 1;
+    rbit <= 1;
+    waddr <= 2;
+    wdat <= x"d2";
+    pulse;
+    assert rdat = '0' severity failure;
+
+    raddr <= 1;
+    rbit <= 7;
+    waddr <= 3;
+    wdat <= x"c3";
+    pulse;
+    assert rdat = '1' severity failure;
+
+    raddr <= 3;
+    rbit <= 7;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = '1' severity failure;
+
+    raddr <= 3;
+    rbit <= 5;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/tb_dpram2r.vhdl b/testsuite/synth/mem2d01/tb_dpram2r.vhdl
new file mode 100644
index 000000000..854e5662a
--- /dev/null
+++ b/testsuite/synth/mem2d01/tb_dpram2r.vhdl
@@ -0,0 +1,72 @@
+entity tb_dpram2r is
+end tb_dpram2r;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram2r is
+  signal raddr : natural range 0 to 3;
+  signal rnib : natural range 0 to 1;
+  signal rdat : std_logic_vector (3 downto 0);
+  signal waddr : natural range 0 to 3;
+  signal wdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram2r
+    port map (raddr => raddr, rnib => rnib, rdat => rdat,
+              waddr => waddr, wdat => wdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    raddr <= 0;
+    rnib <= 0;
+    waddr <= 1;
+    wdat <= x"e1";
+    pulse;
+
+    raddr <= 1;
+    rnib <= 0;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = x"1" severity failure;
+
+    raddr <= 1;
+    rnib <= 1;
+    waddr <= 2;
+    wdat <= x"d2";
+    pulse;
+    assert rdat = x"e" severity failure;
+
+    raddr <= 2;
+    rnib <= 1;
+    waddr <= 3;
+    wdat <= x"c3";
+    pulse;
+    assert rdat = x"d" severity failure;
+
+    raddr <= 3;
+    rnib <= 0;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = x"3" severity failure;
+
+    raddr <= 3;
+    rnib <= 1;
+    waddr <= 0;
+    wdat <= x"f0";
+    pulse;
+    assert rdat = x"c" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/tb_dpram2w.vhdl b/testsuite/synth/mem2d01/tb_dpram2w.vhdl
new file mode 100644
index 000000000..80850d92f
--- /dev/null
+++ b/testsuite/synth/mem2d01/tb_dpram2w.vhdl
@@ -0,0 +1,92 @@
+entity tb_dpram2w is
+end tb_dpram2w;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_dpram2w is
+  signal waddr : natural range 0 to 3;
+  signal wnib : natural range 0 to 1;
+  signal wdat : std_logic_vector (3 downto 0);
+  signal raddr : natural range 0 to 3;
+  signal rdat : std_logic_vector(7 downto 0);
+  signal clk : std_logic;
+begin
+  dut: entity work.dpram2w
+    port map (waddr => waddr, wnib => wnib, wdat => wdat,
+              raddr => raddr, rdat => rdat,
+              clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    waddr <= 0;
+    wnib <= 0;
+    wdat <= x"0";
+    raddr <= 1;
+    pulse;
+
+    waddr <= 0;
+    wnib <= 1;
+    wdat <= x"f";
+    raddr <= 1;
+    pulse;
+
+    waddr <= 1;
+    wnib <= 1;
+    wdat <= x"e";
+    raddr <= 0;
+    pulse;
+    assert rdat = x"f0" severity failure;
+
+    waddr <= 1;
+    wnib <= 0;
+    wdat <= x"1";
+    raddr <= 0;
+    pulse;
+    assert rdat = x"f0" severity failure;
+
+    waddr <= 3;
+    wnib <= 0;
+    wdat <= x"3";
+    raddr <= 1;
+    pulse;
+    assert rdat = x"e1" severity failure;
+
+    waddr <= 3;
+    wnib <= 1;
+    wdat <= x"c";
+    raddr <= 1;
+    pulse;
+    assert rdat = x"e1" severity failure;
+
+    waddr <= 2;
+    wnib <= 1;
+    wdat <= x"d";
+    raddr <= 3;
+    pulse;
+    assert rdat = x"c3" severity failure;
+
+    waddr <= 2;
+    wnib <= 0;
+    wdat <= x"2";
+    raddr <= 3;
+    pulse;
+    assert rdat = x"c3" severity failure;
+
+    waddr <= 1;
+    wnib <= 0;
+    wdat <= x"1";
+    raddr <= 2;
+    pulse;
+    assert rdat = x"d2" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/mem2d01/testsuite.sh b/testsuite/synth/mem2d01/testsuite.sh
new file mode 100755
index 000000000..3f49885dd
--- /dev/null
+++ b/testsuite/synth/mem2d01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in dpram1r dpram2r dpram2w; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"