Add testcase for #371

2 files changed, 38 insertions, 0 deletions

diff --git a/testsuite/gna/issue371/test_string.vhdl b/testsuite/gna/issue371/test_string.vhdl
new file mode 100644
index 000000000..b178a31b8
--- /dev/null
+++ b/testsuite/gna/issue371/test_string.vhdl
@@ -0,0 +1,20 @@
+-- VHDL source file
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test_string is
+end entity;
+
+architecture rtl of test_string is
+    signal clk  : std_logic := '1';
+    signal test : string (1 to 11) := "Hello World";
+begin
+    clk <= not clk after 10 ns;
+    p_test : process
+    begin
+        wait for 1 us;
+        test <= "hello world";
+        wait;
+    end process;
+end rtl;
diff --git a/testsuite/gna/issue371/testsuite.sh b/testsuite/gna/issue371/testsuite.sh
new file mode 100755
index 000000000..147ab74c4
--- /dev/null
+++ b/testsuite/gna/issue371/testsuite.sh
@@ -0,0 +1,18 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze test_string.vhdl
+elab test_string
+
+if ghdl_has_feature test_string ghw; then
+  simulate test_string --wave=sim.ghw --stop-time=20ns
+fi
+
+clean
+if [ $# -eq 0 ]; then
+  rm -f sim.ghw
+fi
+
+
+echo "Test successful"