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| author | Christos Gentsos <christos.gentsos@cern.ch> | 2019-06-05 15:15:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-06 18:47:05 +0200 |
| commit | 2c72cffb32c5bfc081c4a182654f2c46bb288db6 (patch) | |
| tree | 65ef32780d6253aea67dde8cc425269645a0d9e8 | |
| parent | 5bafb1b3aaf6edebb5308a9c361844b4d4438b6a (diff) | |
| download | ghdl-2c72cffb32c5bfc081c4a182654f2c46bb288db6.tar.gz ghdl-2c72cffb32c5bfc081c4a182654f2c46bb288db6.tar.bz2 ghdl-2c72cffb32c5bfc081c4a182654f2c46bb288db6.zip | |
synth: handle numeric_std subtraction (addition was already there)
| -rw-r--r-- | src/synth/synth-expr.adb | 11 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 20 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
3 files changed, 38 insertions, 0 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index d13fc6cfc..d8645eeaf 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -479,6 +479,17 @@ package body Synth.Expr is Synth_Uresize (Right, Get_Width (Left))), Create_Res_Range (Left, L)); end; + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => + -- "-" (Unsigned, Natural) + declare + L : constant Net := Get_Net (Left); + begin + return Create_Value_Net + (Build_Dyadic (Build_Context, Id_Sub, + L, + Synth_Uresize (Right, Get_Width (Left))), + Create_Res_Range (Left, L)); + end; when Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat => -- "=" (Unsigned, Natural) return Create_Value_Net diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index c42fb59b4..0c76ff533 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -52,6 +52,24 @@ package body Vhdl.Ieee.Numeric is (others => (others => Iir_Predefined_None))); + Sub_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + Eq_Patterns : constant Binary_Pattern_Type := (Pkg_Std => (Type_Unsigned => @@ -221,6 +239,8 @@ package body Vhdl.Ieee.Numeric is case Get_Identifier (Decl) is when Name_Op_Plus => Handle_Binary (Add_Patterns); + when Name_Op_Minus => + Handle_Binary (Sub_Patterns); when Name_Op_Equality => Handle_Binary (Eq_Patterns); when Name_To_Bstring diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 228b58d68..3f4213ca7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4815,6 +4815,13 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int, Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns, + Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int, + Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Uns, Iir_Predefined_Ieee_Numeric_Std_Eq_Uns_Nat, Iir_Predefined_Ieee_Numeric_Std_Eq_Nat_Uns, |