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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-20 08:08:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-20 08:08:51 +0200 |
| commit | 25cee57f889ecf1d97c64cd278c6a1e60b7d77bd (patch) | |
| tree | 41ddf230c22e3de0df59f40a0bd7ca06e6366d84 | |
| parent | af3c9bd03c53d1ac91d35171317b8b8e8f682d89 (diff) | |
| download | ghdl-25cee57f889ecf1d97c64cd278c6a1e60b7d77bd.tar.gz ghdl-25cee57f889ecf1d97c64cd278c6a1e60b7d77bd.tar.bz2 ghdl-25cee57f889ecf1d97c64cd278c6a1e60b7d77bd.zip | |
synth: add more locations.
| -rw-r--r-- | src/synth/synth-expr.adb | 1 | ||||
| -rw-r--r-- | src/synth/synth-insts.adb | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 8c051fd00..e4e12f6e5 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -960,6 +960,7 @@ package body Synth.Expr is Voff := Dyn_Index_To_Offset (Bnd, Idx_Val, Name); Voff := Build_Memidx (Get_Build (Syn_Inst), Voff, W, Bnd.Len, Width (Clog2 (Uns64 (W * Bnd.Len)))); + Set_Location (Voff, Name); Off := 0; end if; end Synth_Indexed_Name; diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 2f6842eb4..055d9b015 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -877,6 +877,7 @@ package body Synth.Insts is Set_Instance_Module (Syn_Inst, Inst.M); Self_Inst := Get_Self_Instance (Inst.M); + Set_Location (Self_Inst, Entity); -- Create wires for inputs and outputs. Inter := Get_Port_Chain (Entity); |