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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-10 07:43:56 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-10 07:43:56 +0200 |
| commit | 1ed07f150ef05cf71e04a626c403f28ad1510358 (patch) | |
| tree | 4393ab75aac8a3d4fbf4028529615f5e7087fb50 | |
| parent | 8be1c7f59f6f824ab3a90f9fe3767984c50c45b6 (diff) | |
| download | ghdl-1ed07f150ef05cf71e04a626c403f28ad1510358.tar.gz ghdl-1ed07f150ef05cf71e04a626c403f28ad1510358.tar.bz2 ghdl-1ed07f150ef05cf71e04a626c403f28ad1510358.zip | |
synth-oper: handle more operators.
| -rw-r--r-- | src/synth/synth-oper.adb | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 82a23f310..4ccb85ff7 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -487,12 +487,14 @@ package body Synth.Oper is raise Internal_Error; end if; - when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int => -- "+" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Add); when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl => + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv => -- "+" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Add, True); when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int => @@ -1043,7 +1045,8 @@ package body Synth.Oper is end if; return Create_Value_Net (Get_Net (L), Create_Res_Bound (L)); end; - when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns => + when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => declare Arg : constant Value_Acc := Get_Value (Subprg_Inst, Param1); Size : constant Value_Acc := Get_Value (Subprg_Inst, Param2); |