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author | Tristan Gingold <tgingold@free.fr> | 2018-09-23 07:49:46 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-09-23 07:50:53 +0200 |
commit | 1cbe9b82221a2da874ab2b12463b42eee5cfaaa7 (patch) | |
tree | caae65343ce360532bf370327b252a1728c6057e | |
parent | ee9f2600d1272470abc4ebbf09f7469e1656c39c (diff) | |
download | ghdl-1cbe9b82221a2da874ab2b12463b42eee5cfaaa7.tar.gz ghdl-1cbe9b82221a2da874ab2b12463b42eee5cfaaa7.tar.bz2 ghdl-1cbe9b82221a2da874ab2b12463b42eee5cfaaa7.zip |
Add reproducer for #643
-rw-r--r-- | src/vhdl/translate/trans-chap7.adb | 2 | ||||
-rw-r--r-- | testsuite/gna/issue643/ent.vhdl | 31 | ||||
-rw-r--r-- | testsuite/gna/issue643/repro.vhdl | 13 | ||||
-rwxr-xr-x | testsuite/gna/issue643/testsuite.sh | 14 |
4 files changed, 60 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index 1d385ab95..614f993f3 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -2947,6 +2947,8 @@ package body Trans.Chap7 is Dest := Chap3.Slice_Base (Base_Ptr, Aggr_Type, New_Obj_Value (Var_Index)); Translate_Assign (Dest, Expr, Get_Type (Expr)); + -- FIXME: handle non-static expression type (at least for + -- choice by range). Len := Eval_Discrete_Type_Length (Get_Index_Type (Get_Type (Expr), 0)); New_Assign_Stmt diff --git a/testsuite/gna/issue643/ent.vhdl b/testsuite/gna/issue643/ent.vhdl new file mode 100644 index 000000000..07b368f6e --- /dev/null +++ b/testsuite/gna/issue643/ent.vhdl @@ -0,0 +1,31 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is +end entity; + +architecture a of test is + type RegisterNames is ( + LENGTH, + PATTERN_0, PATTERN_1, + COLOR_0, COLOR_1, COLOR_2, COLOR_3 + ); + type RegisterFile is array(RegisterNames) of std_logic_vector(31 downto 0); + + signal Reg : RegisterFile := ( + LENGTH => 32d"4", + PATTERN_0 => ( + 1 downto 0 => "01", -- line 18: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32 + 3 downto 2 => "11", -- line 19: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32 + 5 downto 4 => "01", -- line 20: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32 + 7 downto 6 => "10", -- line 21: can't match string literal with type anonymous enumeration subtype defined at std_logic_1164.v08:89:32 + others => '0' + ), + COLOR_0 => x"----_00_00", + COLOR_1 => x"----_00_FF", + COLOR_2 => x"----_FF_33", + COLOR_3 => x"----_CC_99", + others => (others => '0') + ); +begin +end architecture; diff --git a/testsuite/gna/issue643/repro.vhdl b/testsuite/gna/issue643/repro.vhdl new file mode 100644 index 000000000..aeb8d06ae --- /dev/null +++ b/testsuite/gna/issue643/repro.vhdl @@ -0,0 +1,13 @@ +entity repro is +end entity; + +architecture a of repro is + constant C_PATTERN_0 : bit_vector(31 downto 0) := ( + 1 downto 0 => "01", + 3 downto 2 => "11", + 5 downto 4 => "01", + 7 downto 6 => "10", + others => '0' + ); +begin +end architecture; diff --git a/testsuite/gna/issue643/testsuite.sh b/testsuite/gna/issue643/testsuite.sh new file mode 100755 index 000000000..e132bd00e --- /dev/null +++ b/testsuite/gna/issue643/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate repro + +analyze ent.vhdl +elab_simulate test + +clean + +echo "Test successful" |