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author | Tristan Gingold <tgingold@free.fr> | 2021-09-29 06:25:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-09-29 06:25:52 +0200 |
commit | 1c74b6723d16f4379676dd4753c60a5268a9ae1d (patch) | |
tree | 753a91200cda120e7d37c0c9c00e18d184b02744 | |
parent | e3ed9e2315c26c1262ba4360fca731fc69b9ad5b (diff) | |
download | ghdl-1c74b6723d16f4379676dd4753c60a5268a9ae1d.tar.gz ghdl-1c74b6723d16f4379676dd4753c60a5268a9ae1d.tar.bz2 ghdl-1c74b6723d16f4379676dd4753c60a5268a9ae1d.zip |
testsuite/gna: add a test for #1881
-rw-r--r-- | testsuite/gna/issue1881/mcve.vhdl | 64 | ||||
-rw-r--r-- | testsuite/gna/issue1881/mcve2.vhdl | 20 | ||||
-rwxr-xr-x | testsuite/gna/issue1881/testsuite.sh | 19 |
3 files changed, 103 insertions, 0 deletions
diff --git a/testsuite/gna/issue1881/mcve.vhdl b/testsuite/gna/issue1881/mcve.vhdl new file mode 100644 index 000000000..e05c7a3dd --- /dev/null +++ b/testsuite/gna/issue1881/mcve.vhdl @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mcve is +end mcve; + +architecture sim of mcve is + constant clock_period : time := 10 ns; + constant width_in : natural := 11; -- 12 bits + constant last_stage : natural := 5; + + signal v_clk : std_logic := '0'; + signal v_rst : std_logic; + + signal counter : unsigned (width_in downto 0); + + subtype stage_reg_t is std_logic_vector (width_in downto 0); + type stage_regs_t is array (0 to last_stage) of stage_reg_t; + signal stage_reg : stage_regs_t; + +begin + + v_clk <= NOT v_clk AFTER clock_period/2; + + process is + begin + v_rst <= '1'; + wait for 20 ns; + v_rst <= '0'; + wait; + end process; + + -- Generate some data that changes with time so that we can see the latency + -- through the module. + process (v_clk) is + begin + if rising_edge (v_clk) then + if v_rst = '1' then + counter <= (others => '0'); + else + counter <= counter + 1; + end if; + end if; + end process; + + -- First stage: + process (v_clk) is + begin + if rising_edge (v_clk) then + stage_reg (0) <= std_logic_vector(counter); + end if; + end process; + + g_stages: for ii in 1 to last_stage generate + process (v_clk) is + begin + if rising_edge (v_clk) then + stage_reg (ii) <= stage_reg (ii - 1); + end if; + end process; + end generate g_stages; + +end sim; diff --git a/testsuite/gna/issue1881/mcve2.vhdl b/testsuite/gna/issue1881/mcve2.vhdl new file mode 100644 index 000000000..8210017ee --- /dev/null +++ b/testsuite/gna/issue1881/mcve2.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mcve2 is +end; + +architecture sim of mcve2 is + constant width_in : natural := 11; -- 12 bits + constant last_stage : natural := 5; + + signal v_clk : std_logic := '0'; + signal v_rst : std_logic; + + subtype stage_reg_t is std_logic_vector (width_in downto 0); + type stage_regs_t is array (0 to last_stage) of stage_reg_t; + signal stage_reg : stage_regs_t; + +begin + +end sim; diff --git a/testsuite/gna/issue1881/testsuite.sh b/testsuite/gna/issue1881/testsuite.sh new file mode 100755 index 000000000..b938a6322 --- /dev/null +++ b/testsuite/gna/issue1881/testsuite.sh @@ -0,0 +1,19 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze mcve.vhdl +elab mcve +if ghdl_has_feature mcve vcd; then + simulate mcve --vcd=mcve.vcd --stop-time=1us + + if ! grep -q "stage_reg is not handled" mcve.vcd; then + echo "error: stage_reg is not dumpable" + exit 1; + fi +fi + +clean +rm -f mcve.vcd + +echo "Test successful" |