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authorTristan Gingold <tgingold@free.fr>2017-03-07 05:51:42 +0100
committerTristan Gingold <tgingold@free.fr>2017-03-09 20:42:57 +0100
commit1aacfb6dc49537a242ac6648664784f2282621d9 (patch)
treebe228c4c1f0e1b8998252a8e1d6492f5b9aa3a66
parent101dd876888f9531cea6657e63706cb43d7c7a67 (diff)
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Add testcase for #300
-rw-r--r--testsuite/gna/issue300/test_bench.vhdl49
-rwxr-xr-xtestsuite/gna/issue300/testsuite.sh12
2 files changed, 61 insertions, 0 deletions
diff --git a/testsuite/gna/issue300/test_bench.vhdl b/testsuite/gna/issue300/test_bench.vhdl
new file mode 100644
index 000000000..acd40f644
--- /dev/null
+++ b/testsuite/gna/issue300/test_bench.vhdl
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity inner is
+ port (
+ clk : in std_logic;
+ inner_counter : in std_logic_vector(6 downto 0));
+end inner;
+
+architecture default of inner is
+begin
+ assert now < 1 ns or inner_counter (6) /= 'U' severity error;
+ assert inner_counter (6) /= 'U' severity error;
+ --do something
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test_bench is
+end test_bench;
+
+architecture default of test_bench is
+ signal clk : std_logic := '0';
+ signal counter : unsigned(7 downto 0) := (others => '0');
+
+begin
+
+ i0: entity work.inner port map (
+ clk => clk,
+ inner_counter => std_logic_vector(counter(6 downto 0)));
+
+ process
+ begin
+ clk <= '1';
+ wait for 1 ns;
+ clk <= '0';
+ wait for 1 ns;
+ end process;
+
+ process(clk)
+ begin
+ if rising_edge(clk) then
+ counter <= counter + 1;
+ end if;
+ end process;
+
+end default;
diff --git a/testsuite/gna/issue300/testsuite.sh b/testsuite/gna/issue300/testsuite.sh
new file mode 100755
index 000000000..84c6ae773
--- /dev/null
+++ b/testsuite/gna/issue300/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze test_bench.vhdl
+elab_simulate test_bench --stop-time=10ns
+
+# To check: generate .ghw, check for no 'U'
+
+clean
+
+echo "Test successful"