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| author | Tristan Gingold <tgingold@free.fr> | 2020-06-26 18:14:52 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-06-26 19:48:44 +0200 | 
| commit | 19268309ee768de9c78f11e86071aaa9b3b28a06 (patch) | |
| tree | b73883f453a2e63937ebae23fa926452b50efc20 | |
| parent | c96c4bd50b89806af87fd85430be544a04bdb5c9 (diff) | |
| download | ghdl-19268309ee768de9c78f11e86071aaa9b3b28a06.tar.gz ghdl-19268309ee768de9c78f11e86071aaa9b3b28a06.tar.bz2 ghdl-19268309ee768de9c78f11e86071aaa9b3b28a06.zip | |
testsuite/gna: add tests for #1379
| -rw-r--r-- | testsuite/gna/issue1379/bar.vhdl | 36 | ||||
| -rw-r--r-- | testsuite/gna/issue1379/bar0.vhdl | 35 | ||||
| -rw-r--r-- | testsuite/gna/issue1379/bar1.vhdl | 35 | ||||
| -rw-r--r-- | testsuite/gna/issue1379/bar2.vhdl | 11 | ||||
| -rw-r--r-- | testsuite/gna/issue1379/bar3.vhdl | 24 | ||||
| -rw-r--r-- | testsuite/gna/issue1379/bar4.vhdl | 35 | ||||
| -rwxr-xr-x | testsuite/gna/issue1379/testsuite.sh | 17 | 
7 files changed, 193 insertions, 0 deletions
| diff --git a/testsuite/gna/issue1379/bar.vhdl b/testsuite/gna/issue1379/bar.vhdl new file mode 100644 index 000000000..391870d3b --- /dev/null +++ b/testsuite/gna/issue1379/bar.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity foo is +  generic ( +    LENGTH : natural +    ); +  port ( +    input : in std_logic_vector(LENGTH - 1 downto 0) +    ); +end foo; + +architecture behave of foo is +begin +end behave; + +library ieee; +use ieee.std_logic_1164.all; + +entity bar is +end entity bar; + +architecture behave of bar is +  component foo is +  port ( +    input : in std_logic_vector(7 downto 0) +    ); +  end component; + +begin + +  my_foo : foo +    port map ( +      input => (others => '0') +      ); +end behave; diff --git a/testsuite/gna/issue1379/bar0.vhdl b/testsuite/gna/issue1379/bar0.vhdl new file mode 100644 index 000000000..303d80516 --- /dev/null +++ b/testsuite/gna/issue1379/bar0.vhdl @@ -0,0 +1,35 @@ +entity foo is +  generic ( +    LENGTH : natural +    ); +  port ( +    input : in bit_vector(LENGTH - 1 downto 0) +    ); +end foo; + +architecture behave of foo is +begin +end behave; + +entity bar is +end entity bar; + +architecture behave of bar is +  component foo is +  port ( +    input : in bit_vector(7 downto 0) +    ); +  end component; + +begin + +  my_foo : foo +    port map ( +      input => (others => '0') +      ); +end behave; + +configuration cfg of bar is +  for cfg +  end for; +end cfg; diff --git a/testsuite/gna/issue1379/bar1.vhdl b/testsuite/gna/issue1379/bar1.vhdl new file mode 100644 index 000000000..1fac5c2ba --- /dev/null +++ b/testsuite/gna/issue1379/bar1.vhdl @@ -0,0 +1,35 @@ +entity foo is +  generic ( +    LENGTH : natural +    ); +  port ( +    input : in bit_vector(LENGTH - 1 downto 0) +    ); +end foo; + +architecture behave of foo is +begin +end behave; + +entity bar is +end entity bar; + +architecture behave of bar is +  component foo is +  port ( +    input : in bit_vector(7 downto 0) +    ); +  end component; + +begin + +  my_foo : foo +    port map ( +      input => (others => '0') +      ); +end behave; + +configuration cfg of bar is +  for behave +  end for; +end cfg; diff --git a/testsuite/gna/issue1379/bar2.vhdl b/testsuite/gna/issue1379/bar2.vhdl new file mode 100644 index 000000000..7b367332d --- /dev/null +++ b/testsuite/gna/issue1379/bar2.vhdl @@ -0,0 +1,11 @@ +entity bar2 is +end bar2; + +architecture behav of bar2 is +  function f(v : natural) return natural is +  begin +    return 1; +  end f; +begin +  assert f(v => open) = 1; +end behav; diff --git a/testsuite/gna/issue1379/bar3.vhdl b/testsuite/gna/issue1379/bar3.vhdl new file mode 100644 index 000000000..20665a853 --- /dev/null +++ b/testsuite/gna/issue1379/bar3.vhdl @@ -0,0 +1,24 @@ +entity foo3 is +  generic ( +    LENGTH : natural +    ); +  port ( +    input : in bit_vector(LENGTH - 1 downto 0) +    ); +end foo3; + +architecture behave of foo3 is +begin +end behave; + +entity bar3 is +end entity bar3; + +architecture behave of bar3 is +begin + +  my_foo : entity work.foo3 +    port map ( +      input => (others => '0') +      ); +end behave; diff --git a/testsuite/gna/issue1379/bar4.vhdl b/testsuite/gna/issue1379/bar4.vhdl new file mode 100644 index 000000000..6aaf26791 --- /dev/null +++ b/testsuite/gna/issue1379/bar4.vhdl @@ -0,0 +1,35 @@ +entity foo4 is +  port ( +    input : in bit_vector(1 downto 0) +    ); +end foo4; + +architecture behave of foo4 is +begin +end behave; + +entity bar4 is +end entity bar4; + +architecture behave of bar4 is +  component foo4 is +  port ( +    input : in natural +    ); +  end component; + +begin + +  my_foo : foo4 +    port map ( +      input => 0 +      ); +end behave; + +configuration cfg of bar4 is +  for behave +    for my_foo : foo4 +      use open; +    end for; +  end for; +end cfg; diff --git a/testsuite/gna/issue1379/testsuite.sh b/testsuite/gna/issue1379/testsuite.sh new file mode 100755 index 000000000..2133a4e86 --- /dev/null +++ b/testsuite/gna/issue1379/testsuite.sh @@ -0,0 +1,17 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze bar.vhdl +elab_failure bar + +analyze_failure bar0.vhdl + +analyze_failure bar2.vhdl +analyze_failure bar3.vhdl + +analyze bar4.vhdl + +clean + +echo "Test successful" | 
