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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:37:46 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-11 18:38:06 +0100 |
| commit | 17035deb83dd13aa9c9fc09e28c70b983aeeca59 (patch) | |
| tree | 8b128556c81d43696c8c94f47f7d41fc2b8554c4 | |
| parent | c055dacd817234fd25ba20d5a5dac9df532c415b (diff) | |
| download | ghdl-17035deb83dd13aa9c9fc09e28c70b983aeeca59.tar.gz ghdl-17035deb83dd13aa9c9fc09e28c70b983aeeca59.tar.bz2 ghdl-17035deb83dd13aa9c9fc09e28c70b983aeeca59.zip | |
vhdl-ieee-std_logic_unsigned: recognize more operations.
| -rw-r--r-- | src/synth/synth-oper.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 4e8c434c4..1a3a10bf5 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1070,6 +1070,7 @@ package body Synth.Oper is -- ">" (Unsigned, Unsigned) [resize] return Synth_Compare_Uns_Uns (Id_Ugt, Expr_Typ); when Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Slv_Int | Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Uns_Nat => -- ">" (Unsigned, Natural) return Synth_Compare_Uns_Nat (Id_Ugt, Expr_Typ); diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index c3b30be8e..69893b954 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -54,6 +54,18 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, others => Iir_Predefined_None); + Gt_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Int_Slv, + others => Iir_Predefined_None); + + Ge_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Int_Slv, + others => Iir_Predefined_None); + Add_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, @@ -174,6 +186,10 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Res := Handle_Binary (Lt_Patterns, None_Patterns); when Name_Op_Less_Equal => Res := Handle_Binary (Le_Patterns, None_Patterns); + when Name_Op_Greater => + Res := Handle_Binary (Gt_Patterns, None_Patterns); + when Name_Op_Greater_Equal => + Res := Handle_Binary (Ge_Patterns, None_Patterns); when Name_Op_Plus => Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); when Name_Op_Minus => |