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author | Tristan Gingold <tgingold@free.fr> | 2020-05-02 09:44:36 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-05-02 09:44:36 +0200 |
commit | 101d88efa3b5fa6ec5b1e647cdf49650ebb606f1 (patch) | |
tree | 58651898be00ebdf170cfa0523ac79de13bb80e9 | |
parent | db7ef6818edba6f7210e2fd6761333cd1131b25e (diff) | |
download | ghdl-101d88efa3b5fa6ec5b1e647cdf49650ebb606f1.tar.gz ghdl-101d88efa3b5fa6ec5b1e647cdf49650ebb606f1.tar.bz2 ghdl-101d88efa3b5fa6ec5b1e647cdf49650ebb606f1.zip |
testsuite/gna: add tests for #1274
-rw-r--r-- | testsuite/gna/issue1274/issue.vhdl | 16 | ||||
-rw-r--r-- | testsuite/gna/issue1274/issue93.vhdl | 13 | ||||
-rw-r--r-- | testsuite/gna/issue1274/repro2.vhdl | 16 | ||||
-rw-r--r-- | testsuite/gna/issue1274/repro3.vhdl | 16 | ||||
-rw-r--r-- | testsuite/gna/issue1274/repro4.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/gna/issue1274/testsuite.sh | 14 |
6 files changed, 104 insertions, 0 deletions
diff --git a/testsuite/gna/issue1274/issue.vhdl b/testsuite/gna/issue1274/issue.vhdl new file mode 100644 index 000000000..4326dd62c --- /dev/null +++ b/testsuite/gna/issue1274/issue.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity issue is + port (foo : out unsigned (1 downto 0); + bar : out unsigned (2 downto 0); + foobar : out unsigned (4 downto 0)); +end entity issue; + +architecture beh of issue is +begin + assert 5ub"11_000" = unsigned'(b"11_000"); + foobar <= 5ub"11_000" + 5ub"00_000"; -- works + (foo, bar) <= 5ub"11_000" + 5ub"00_000"; -- crashes +end architecture; diff --git a/testsuite/gna/issue1274/issue93.vhdl b/testsuite/gna/issue1274/issue93.vhdl new file mode 100644 index 000000000..30e75bcd7 --- /dev/null +++ b/testsuite/gna/issue1274/issue93.vhdl @@ -0,0 +1,13 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity issue93 is + port (foo : out std_logic; + bar : out std_logic); +end ; + +architecture beh of issue93 is +begin + (foo, bar) <= "10" + "01"; -- crashes +end architecture; diff --git a/testsuite/gna/issue1274/repro2.vhdl b/testsuite/gna/issue1274/repro2.vhdl new file mode 100644 index 000000000..d3b1655cf --- /dev/null +++ b/testsuite/gna/issue1274/repro2.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro2 is +end ; + +architecture beh of repro2 is +begin + process + variable foo, bar : std_logic; + begin + (foo, bar) := "10" + "01"; -- crashes + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1274/repro3.vhdl b/testsuite/gna/issue1274/repro3.vhdl new file mode 100644 index 000000000..d7fc2e56c --- /dev/null +++ b/testsuite/gna/issue1274/repro3.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro3 is +end ; + +architecture beh of repro3 is +begin + process + variable foo, bar : std_logic; + begin + (foo, bar) := "10"; -- crashes + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1274/repro4.vhdl b/testsuite/gna/issue1274/repro4.vhdl new file mode 100644 index 000000000..2fbe2cd16 --- /dev/null +++ b/testsuite/gna/issue1274/repro4.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity repro4 is +end ; + +architecture beh of repro4 is + type str_acc is access string; + type bv_acc is access bit_Vector; + + function f return str_acc is + begin + return new String'("abc"); + end f; + + function f return bv_acc is + begin + return new bit_vector'("001"); + end f; + +begin + process + variable foo, bar : std_logic; + begin + f.all := "010"; + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue1274/testsuite.sh b/testsuite/gna/issue1274/testsuite.sh new file mode 100755 index 000000000..cf6a53bd8 --- /dev/null +++ b/testsuite/gna/issue1274/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure issue.vhdl + +export GHDL_STD_FLAGS="" +analyze_failure issue93.vhdl +analyze_failure repro2.vhdl +analyze_failure repro3.vhdl +analyze_failure repro4.vhdl + +echo "Test successful" |