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| author | Tristan Gingold <tgingold@free.fr> | 2021-03-17 18:44:41 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-03-17 18:44:41 +0100 |
| commit | 0d8f155d3c9e5413a42984f0f290c71ab89a71ba (patch) | |
| tree | 5716d599913af51e021c542c6c39498f49191441 | |
| parent | 009f0b955b5084594b6912d261405fd1936750f9 (diff) | |
| download | ghdl-0d8f155d3c9e5413a42984f0f290c71ab89a71ba.tar.gz ghdl-0d8f155d3c9e5413a42984f0f290c71ab89a71ba.tar.bz2 ghdl-0d8f155d3c9e5413a42984f0f290c71ab89a71ba.zip | |
std_names: add Name_Loc
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index df2e399ce..b9eeea05e 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -684,6 +684,7 @@ package body Std_Names is Def ("anyconst", Name_Anyconst); Def ("anyseq", Name_Anyseq); Def ("gclk", Name_Gclk); + Def ("loc", Name_Loc); -- Verilog directives Def ("define", Name_Define); diff --git a/src/std_names.ads b/src/std_names.ads index bd6429bff..46b7542df 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -769,7 +769,8 @@ package Std_Names is Name_Anyconst : constant Name_Id := Name_First_Synthesis + 002; Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; - Name_Last_Synthesis : constant Name_Id := Name_Gclk; + Name_Loc : constant Name_Id := Name_First_Synthesis + 005; + Name_Last_Synthesis : constant Name_Id := Name_Loc; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; |