synth-disp_vhdl: do not wrap inout ports. For #1166

8 files changed, 51 insertions, 17 deletions

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 78954af95..9280d619c 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -26,12 +26,14 @@ package body Netlists.Builders is
    function Create_Input (Id : String; W : Width := 0) return Port_Desc is
    begin
       return (Name => New_Sname_Artificial (Get_Identifier (Id), No_Sname),
+              Is_Inout => False,
               W => W);
    end Create_Input;
 
    function Create_Output (Id : String; W : Width := 0) return Port_Desc is
    begin
       return (Name => New_Sname_Artificial (Get_Identifier (Id), No_Sname),
+              Is_Inout => False,
               W => W);
    end Create_Output;
 
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index f4e8e49f7..99a87d2f4 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -1297,6 +1297,8 @@ package body Netlists.Disp_Vhdl is
             Put ("in");
          when Port_Out =>
             Put ("out");
+         when Port_Inout =>
+            raise Internal_Error;
       end case;
       Put (' ');
       Put_Type (Desc.W);
diff --git a/src/synth/netlists-dump.adb b/src/synth/netlists-dump.adb
index b3effff05..8a018788d 100644
--- a/src/synth/netlists-dump.adb
+++ b/src/synth/netlists-dump.adb
@@ -221,6 +221,8 @@ package body Netlists.Dump is
             Put ("input");
          when Port_Out =>
             Put ("output");
+         when Port_Inout =>
+            raise Internal_Error;
       end case;
       Put (' ');
       Dump_Name (Desc.Name);
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index b7577f85c..042091e3c 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -119,6 +119,7 @@ package Netlists.Gates is
    Id_Output  : constant Module_Id := 50;
    Id_Ioutput : constant Module_Id := 51;
    Id_Port    : constant Module_Id := 52;
+   Id_Inout   : constant Module_Id := 53;
 
    --  Note: initial values must be constant nets.
    --
diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb
index 545a4df16..d130b7c1f 100644
--- a/src/synth/netlists.adb
+++ b/src/synth/netlists.adb
@@ -157,7 +157,8 @@ package body Netlists is
    begin
       Ports_Desc := Port_Desc_Table.Last + 1;
       for I in 1 .. Nbr_Inputs + Nbr_Outputs loop
-         Port_Desc_Table.Append ((Name => No_Sname, W => 0));
+         Port_Desc_Table.Append
+           ((Name => No_Sname, Is_Inout => False, W => 0));
       end loop;
 
       Modules_Table.Append
@@ -952,6 +953,7 @@ begin
    pragma Assert (Inputs_Table.Last = No_Input);
 
    Port_Desc_Table.Append ((Name => No_Sname,
+                            Is_Inout => False,
                             W => 0));
    pragma Assert (Port_Desc_Table.Last = No_Port_Desc_Idx);
 
diff --git a/src/synth/netlists.ads b/src/synth/netlists.ads
index 8683d6943..fb02cca17 100644
--- a/src/synth/netlists.ads
+++ b/src/synth/netlists.ads
@@ -125,7 +125,7 @@ package Netlists is
    subtype Width is Uns32;
    No_Width : constant Width := 0;
 
-   type Port_Kind is (Port_In, Port_Out);
+   type Port_Kind is (Port_In, Port_Out, Port_Inout);
 
    --  Each module has a numeric identifier that can be used to easily identify
    --  a module.  Gates (and, or, ...) have reserved identifiers.
@@ -153,9 +153,12 @@ package Netlists is
       --  Name of the port.
       Name : Sname;
 
+      Is_Inout : Boolean;
+
       --  Port width (number of bits).
       W : Width;
    end record;
+   pragma Pack (Port_Desc);
    pragma Convention (C, Port_Desc);
 
    type Port_Desc_Array is array (Port_Idx range <>) of Port_Desc;
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index c5260bf5a..c60a65e59 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -44,13 +44,20 @@ package body Synth.Disp_Vhdl is
       Put_Line (";");
    end Disp_Signal;
 
-   procedure Disp_Ports_As_Signals (M : Module) is
+   procedure Disp_Ports_As_Signals (M : Module)
+   is
+      Desc : Port_Desc;
    begin
       for I in 1 .. Get_Nbr_Inputs (M) loop
          Disp_Signal (Get_Input_Desc (M, I - 1));
       end loop;
       for I in 1 .. Get_Nbr_Outputs (M) loop
-         Disp_Signal (Get_Output_Desc (M, I - 1));
+         Desc := Get_Output_Desc (M, I - 1);
+         if not Desc.Is_Inout then
+            --  inout ports are not prefixed, so they must not be declared
+            --  as signals.
+            Disp_Signal (Desc);
+         end if;
       end loop;
    end Disp_Ports_As_Signals;
 
@@ -439,7 +446,9 @@ package body Synth.Disp_Vhdl is
       Name_Wrap := Name_Table.Get_Identifier ("wrap");
       for P of Ports_Desc (Main) loop
          pragma Assert (Get_Sname_Prefix (P.Name) = No_Sname);
-         Set_Sname_Prefix (P.Name, New_Sname_User (Name_Wrap, No_Sname));
+         if not P.Is_Inout then
+            Set_Sname_Prefix (P.Name, New_Sname_User (Name_Wrap, No_Sname));
+         end if;
       end loop;
 
       Put_Line ("library ieee;");
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index b5f0a58aa..b33df7097 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -59,9 +59,10 @@ package body Synth.Insts is
          when Iir_In_Mode =>
             return Port_In;
          when Iir_Buffer_Mode
-           | Iir_Out_Mode
-           | Iir_Inout_Mode =>
+           | Iir_Out_Mode =>
             return Port_Out;
+         when Iir_Inout_Mode =>
+            return Port_Inout;
          when Iir_Linkage_Mode
            | Iir_Unknown_Mode =>
             raise Synth_Error;
@@ -69,13 +70,15 @@ package body Synth.Insts is
    end Mode_To_Port_Kind;
 
    function Make_Port_Desc (Syn_Inst : Synth_Instance_Acc;
-                            Inter : Node) return Port_Desc
+                            Inter : Node;
+                            Is_Inout : Boolean := False) return Port_Desc
    is
       Val : constant Value_Acc := Get_Value (Syn_Inst, Inter);
       Name : Sname;
    begin
       Name :=  New_Sname_User (Get_Identifier (Inter), No_Sname);
       return (Name => Name,
+              Is_Inout => Is_Inout,
               W => Get_Type_Width (Val.Typ));
    end Make_Port_Desc;
 
@@ -394,7 +397,8 @@ package body Synth.Insts is
             when Port_In =>
                Val := Create_Value_Net (No_Net, Inter_Typ);
                Nbr_Inputs := Nbr_Inputs + 1;
-            when Port_Out =>
+            when Port_Out
+              | Port_Inout =>
                Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
                Nbr_Outputs := Nbr_Outputs + 1;
          end case;
@@ -413,18 +417,22 @@ package body Synth.Insts is
       declare
          Inports : Port_Desc_Array (1 .. Nbr_Inputs);
          Outports : Port_Desc_Array (1 .. Nbr_Outputs);
+         Pkind : Port_Kind;
       begin
          Inter := Get_Port_Chain (Decl);
          Nbr_Inputs := 0;
          Nbr_Outputs := 0;
          while Is_Valid (Inter) loop
-            case Mode_To_Port_Kind (Get_Mode (Inter)) is
+            Pkind := Mode_To_Port_Kind (Get_Mode (Inter));
+            case Pkind is
                when Port_In =>
                   Nbr_Inputs := Nbr_Inputs + 1;
                   Inports (Nbr_Inputs) := Make_Port_Desc (Syn_Inst, Inter);
-               when Port_Out =>
+               when Port_Out
+                 | Port_Inout =>
                   Nbr_Outputs := Nbr_Outputs + 1;
-                  Outports (Nbr_Outputs) := Make_Port_Desc (Syn_Inst, Inter);
+                  Outports (Nbr_Outputs) :=
+                    Make_Port_Desc (Syn_Inst, Inter, Pkind = Port_Inout);
             end case;
             Inter := Get_Chain (Inter);
          end loop;
@@ -731,7 +739,8 @@ package body Synth.Insts is
                            Synth_Input_Assoc
                              (Syn_Inst, Assoc, Inst_Obj.Syn_Inst, Inter));
                   Nbr_Inputs := Nbr_Inputs + 1;
-               when Port_Out =>
+               when Port_Out
+                 | Port_Inout =>
                   Synth_Output_Assoc
                     (Get_Output (Inst, Nbr_Outputs),
                      Syn_Inst, Assoc, Inst_Obj.Syn_Inst, Inter);
@@ -881,7 +890,8 @@ package body Synth.Insts is
             case Mode_To_Port_Kind (Get_Mode (Inter)) is
                when Port_In =>
                   Val := Create_Value_Net (No_Net, Inter_Typ);
-               when Port_Out =>
+               when Port_Out
+                 | Port_Inout =>
                   Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
             end case;
             Create_Object (Sub_Inst, Inter, Val);
@@ -1056,7 +1066,8 @@ package body Synth.Insts is
                      N := Synth_Input_Assoc
                        (Syn_Inst, Assoc, Comp_Inst, Inter);
                      Val := Create_Value_Net (N, Inter_Type);
-                  when Port_Out =>
+                  when Port_Out
+                    | Port_Inout =>
                      Val := Create_Value_Wire (No_Wire_Id, Inter_Type);
                      Create_Component_Wire
                        (Get_Build (Syn_Inst), Assoc_Inter, Val, Inst_Name);
@@ -1261,7 +1272,8 @@ package body Synth.Insts is
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
                Val := Create_Value_Net (No_Net, Inter_Typ);
-            when Port_Out =>
+            when Port_Out
+              | Port_Inout =>
                Val := Create_Value_Wire (No_Wire_Id, Inter_Typ);
          end case;
          Create_Object (Syn_Inst, Inter, Val);
@@ -1425,7 +1437,8 @@ package body Synth.Insts is
             when Port_In =>
                Create_Input_Wire (Self_Inst, Nbr_Inputs, Val);
                Nbr_Inputs := Nbr_Inputs + 1;
-            when Port_Out =>
+            when Port_Out
+              | Port_Inout =>
                Create_Output_Wire
                  (Syn_Inst, Self_Inst, Inter, Nbr_Outputs, Val);
                Nbr_Outputs := Nbr_Outputs + 1;