synth-oper: recognize more operations from std_logic_arith.

5 files changed, 201 insertions, 63 deletions

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 1c94409d0..4f93775a0 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1460,66 +1460,90 @@ class Iir_Predefined:
     Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 477
     Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 478
     Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 479
-    Ieee_Std_Logic_Arith_Lt_Uns_Uns = 480
-    Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 481
-    Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 482
-    Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 483
-    Ieee_Std_Logic_Arith_Lt_Uns_Int = 484
-    Ieee_Std_Logic_Arith_Lt_Int_Uns = 485
-    Ieee_Std_Logic_Arith_Lt_Sgn_Int = 486
-    Ieee_Std_Logic_Arith_Lt_Int_Sgn = 487
-    Ieee_Std_Logic_Arith_Le_Uns_Uns = 488
-    Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 489
-    Ieee_Std_Logic_Arith_Le_Uns_Sgn = 490
-    Ieee_Std_Logic_Arith_Le_Sgn_Uns = 491
-    Ieee_Std_Logic_Arith_Le_Uns_Int = 492
-    Ieee_Std_Logic_Arith_Le_Int_Uns = 493
-    Ieee_Std_Logic_Arith_Le_Sgn_Int = 494
-    Ieee_Std_Logic_Arith_Le_Int_Sgn = 495
-    Ieee_Std_Logic_Arith_Gt_Uns_Uns = 496
-    Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 497
-    Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 498
-    Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 499
-    Ieee_Std_Logic_Arith_Gt_Uns_Int = 500
-    Ieee_Std_Logic_Arith_Gt_Int_Uns = 501
-    Ieee_Std_Logic_Arith_Gt_Sgn_Int = 502
-    Ieee_Std_Logic_Arith_Gt_Int_Sgn = 503
-    Ieee_Std_Logic_Arith_Ge_Uns_Uns = 504
-    Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 505
-    Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 506
-    Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 507
-    Ieee_Std_Logic_Arith_Ge_Uns_Int = 508
-    Ieee_Std_Logic_Arith_Ge_Int_Uns = 509
-    Ieee_Std_Logic_Arith_Ge_Sgn_Int = 510
-    Ieee_Std_Logic_Arith_Ge_Int_Sgn = 511
-    Ieee_Std_Logic_Arith_Eq_Uns_Uns = 512
-    Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 513
-    Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 514
-    Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 515
-    Ieee_Std_Logic_Arith_Eq_Uns_Int = 516
-    Ieee_Std_Logic_Arith_Eq_Int_Uns = 517
-    Ieee_Std_Logic_Arith_Eq_Sgn_Int = 518
-    Ieee_Std_Logic_Arith_Eq_Int_Sgn = 519
-    Ieee_Std_Logic_Arith_Ne_Uns_Uns = 520
-    Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 521
-    Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 522
-    Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 523
-    Ieee_Std_Logic_Arith_Ne_Uns_Int = 524
-    Ieee_Std_Logic_Arith_Ne_Int_Uns = 525
-    Ieee_Std_Logic_Arith_Ne_Sgn_Int = 526
-    Ieee_Std_Logic_Arith_Ne_Int_Sgn = 527
-    Ieee_Std_Logic_Misc_And_Reduce_Slv = 528
-    Ieee_Std_Logic_Misc_And_Reduce_Suv = 529
-    Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 530
-    Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 531
-    Ieee_Std_Logic_Misc_Or_Reduce_Slv = 532
-    Ieee_Std_Logic_Misc_Or_Reduce_Suv = 533
-    Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 534
-    Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 535
-    Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 536
-    Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 537
-    Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 538
-    Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 539
+    Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns = 480
+    Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn = 481
+    Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn = 482
+    Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn = 483
+    Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns = 484
+    Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns = 485
+    Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn = 486
+    Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn = 487
+    Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns = 488
+    Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns = 489
+    Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn = 490
+    Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn = 491
+    Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv = 492
+    Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv = 493
+    Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv = 494
+    Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv = 495
+    Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv = 496
+    Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv = 497
+    Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv = 498
+    Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv = 499
+    Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv = 500
+    Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv = 501
+    Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv = 502
+    Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv = 503
+    Ieee_Std_Logic_Arith_Lt_Uns_Uns = 504
+    Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 505
+    Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 506
+    Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 507
+    Ieee_Std_Logic_Arith_Lt_Uns_Int = 508
+    Ieee_Std_Logic_Arith_Lt_Int_Uns = 509
+    Ieee_Std_Logic_Arith_Lt_Sgn_Int = 510
+    Ieee_Std_Logic_Arith_Lt_Int_Sgn = 511
+    Ieee_Std_Logic_Arith_Le_Uns_Uns = 512
+    Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 513
+    Ieee_Std_Logic_Arith_Le_Uns_Sgn = 514
+    Ieee_Std_Logic_Arith_Le_Sgn_Uns = 515
+    Ieee_Std_Logic_Arith_Le_Uns_Int = 516
+    Ieee_Std_Logic_Arith_Le_Int_Uns = 517
+    Ieee_Std_Logic_Arith_Le_Sgn_Int = 518
+    Ieee_Std_Logic_Arith_Le_Int_Sgn = 519
+    Ieee_Std_Logic_Arith_Gt_Uns_Uns = 520
+    Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 521
+    Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 522
+    Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 523
+    Ieee_Std_Logic_Arith_Gt_Uns_Int = 524
+    Ieee_Std_Logic_Arith_Gt_Int_Uns = 525
+    Ieee_Std_Logic_Arith_Gt_Sgn_Int = 526
+    Ieee_Std_Logic_Arith_Gt_Int_Sgn = 527
+    Ieee_Std_Logic_Arith_Ge_Uns_Uns = 528
+    Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 529
+    Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 530
+    Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 531
+    Ieee_Std_Logic_Arith_Ge_Uns_Int = 532
+    Ieee_Std_Logic_Arith_Ge_Int_Uns = 533
+    Ieee_Std_Logic_Arith_Ge_Sgn_Int = 534
+    Ieee_Std_Logic_Arith_Ge_Int_Sgn = 535
+    Ieee_Std_Logic_Arith_Eq_Uns_Uns = 536
+    Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 537
+    Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 538
+    Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 539
+    Ieee_Std_Logic_Arith_Eq_Uns_Int = 540
+    Ieee_Std_Logic_Arith_Eq_Int_Uns = 541
+    Ieee_Std_Logic_Arith_Eq_Sgn_Int = 542
+    Ieee_Std_Logic_Arith_Eq_Int_Sgn = 543
+    Ieee_Std_Logic_Arith_Ne_Uns_Uns = 544
+    Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 545
+    Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 546
+    Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 547
+    Ieee_Std_Logic_Arith_Ne_Uns_Int = 548
+    Ieee_Std_Logic_Arith_Ne_Int_Uns = 549
+    Ieee_Std_Logic_Arith_Ne_Sgn_Int = 550
+    Ieee_Std_Logic_Arith_Ne_Int_Sgn = 551
+    Ieee_Std_Logic_Misc_And_Reduce_Slv = 552
+    Ieee_Std_Logic_Misc_And_Reduce_Suv = 553
+    Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 554
+    Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 555
+    Ieee_Std_Logic_Misc_Or_Reduce_Slv = 556
+    Ieee_Std_Logic_Misc_Or_Reduce_Suv = 557
+    Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 558
+    Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 559
+    Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 560
+    Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 561
+    Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 562
+    Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 563
 
 Get_Kind = libghdl.vhdl__nodes__get_kind
 Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 1c8560074..c78515e57 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -831,7 +831,10 @@ package body Synth.Oper is
            | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv
-           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv =>
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Uns =>
             --  "+" (Unsigned, Unsigned)
             return Synth_Dyadic_Uns_Uns (Id_Add, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int
@@ -859,7 +862,10 @@ package body Synth.Oper is
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv
-           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log =>
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns =>
             --  "-" (Unsigned, Unsigned)
             return Synth_Dyadic_Uns_Uns (Id_Sub, Left, Right, Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int
@@ -1132,7 +1138,8 @@ package body Synth.Oper is
             --  ">" (Natural, Unsigned) [resize]
             return Synth_Compare_Nat_Uns (Id_Ugt, Expr_Typ);
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Sgn
-           | Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Sgn_Sgn =>
+           | Iir_Predefined_Ieee_Numeric_Std_Match_Gt_Sgn_Sgn
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Sgn =>
             --  ">" (Signed, Signed) [resize]
             return Synth_Compare_Sgn_Sgn (Id_Sgt, Expr_Typ);
          when Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Int
@@ -1507,6 +1514,8 @@ package body Synth.Oper is
                raise Internal_Error;
             end if;
             return Create_Value_Net (Get_Net (L), Create_Res_Bound (L));
+         when Iir_Predefined_Ieee_1164_To_Bit =>
+            return Create_Value_Net (Get_Net (L), Res_Typ);
          when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns
            | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int =>
             return Synth_Conv_Vector (False);
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 6947cb612..58fe96229 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -300,6 +300,8 @@ package body Vhdl.Ieee.Std_Logic_1164 is
                   --  parameter, clear the flag to allow more optimizations.
                   Set_Has_Active_Flag
                     (Get_Interface_Declaration_Chain (Decl), False);
+               when Name_To_Bit =>
+                  Predefined := Iir_Predefined_Ieee_1164_To_Bit;
                when Name_To_Bitvector =>
                   Predefined := Iir_Predefined_Ieee_1164_To_Bitvector;
                when Name_To_Stdulogic =>
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb
index c1d7caccf..ded3ff0c3 100644
--- a/src/vhdl/vhdl-ieee-std_logic_arith.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb
@@ -173,6 +173,80 @@ package body Vhdl.Ieee.Std_Logic_Arith is
          others =>
            (others => Iir_Predefined_None)));
 
+   Sub_Patterns : constant Bin_Pattern_Type :=
+     (Type_Slv =>
+        (Type_Unsigned =>
+           (Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv,
+            Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv,
+            Type_Int =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv,
+            Type_Log =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv),
+         Type_Signed =>
+           (Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv,
+            Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv,
+            Type_Int =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv,
+            Type_Log =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv),
+         Type_Int =>
+           (Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv,
+            Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv,
+            others => Iir_Predefined_None),
+         Type_Log =>
+           (Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv,
+            Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv,
+            others => Iir_Predefined_None)),
+      Type_Signed =>
+        (Type_Signed =>
+           (Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn,
+            Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn,
+            Type_Int =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn,
+            Type_Log =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn),
+         Type_Unsigned =>
+           (Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn,
+            others => Iir_Predefined_None),
+         Type_Int =>
+           (Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn,
+            others => Iir_Predefined_None),
+         Type_Log =>
+           (Type_Signed =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn,
+            others => Iir_Predefined_None)),
+      Type_Unsigned =>
+        (Type_Unsigned =>
+           (Type_Unsigned =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns,
+            Type_Int =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns,
+            Type_Log =>
+              Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns,
+            others => Iir_Predefined_None),
+         Type_Int =>
+            (Type_Unsigned =>
+               Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns,
+             others => Iir_Predefined_None),
+         Type_Log =>
+            (Type_Unsigned =>
+               Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns,
+             others => Iir_Predefined_None),
+         others =>
+           (others => Iir_Predefined_None)));
+
    Lt_Patterns : constant Cmp_Pattern_Type :=
      (Type_Unsigned =>
         (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns,
@@ -378,6 +452,9 @@ package body Vhdl.Ieee.Std_Logic_Arith is
                      when Name_Op_Plus =>
                         Classify_Arg (Decl, Res_Kind);
                         Def := Handle_Bin (Add_Patterns);
+                     when Name_Op_Minus =>
+                        Classify_Arg (Decl, Res_Kind);
+                        Def := Handle_Bin (Sub_Patterns);
                      when Name_Op_Mul =>
                         Classify_Arg (Decl, Res_Kind);
                         Def := Handle_Bin (Mul_Patterns);
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 8b9345d00..323587548 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5822,6 +5822,32 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv,
       Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv,
 
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn,
+
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv,
+
       Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns,
       Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Sgn,
       Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Sgn,