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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-10 07:29:29 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:28:49 +0100 |
| commit | 0984b848d16a9445b019363cfe4be82d123e4e20 (patch) | |
| tree | 68e09d8828819222f42fb8ebe719d4917acda300 | |
| parent | 6eb11dd7c637659881f80cd66e5504b2b057d370 (diff) | |
| download | ghdl-0984b848d16a9445b019363cfe4be82d123e4e20.tar.gz ghdl-0984b848d16a9445b019363cfe4be82d123e4e20.tar.bz2 ghdl-0984b848d16a9445b019363cfe4be82d123e4e20.zip | |
synth: simplify equality tests.
| -rw-r--r-- | src/synth/synth-oper.adb | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 80504713e..6a31efdc5 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -431,8 +431,9 @@ package body Synth.Oper is return Create_Value_Discrete (Boolean'Pos (Left.Scal = Right.Scal), Boolean_Type); end if; - if Left_Typ.Kind = Type_Bit then - pragma Assert (Right.Typ.Kind = Type_Bit); + if Left_Typ = Bit_Type + or else Left_Typ = Logic_Type + then if Is_Const (Left) then return Synth_Bit_Eq_Const (Left, Right, Expr); elsif Is_Const (Right) then |