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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-26 17:05:23 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-26 17:05:23 +0100 |
| commit | 0512b63484398a6220156a989e7bfc6efdc5b038 (patch) | |
| tree | a31e14c20f9290224cbcc9ce39e7544c7de13d71 | |
| parent | 5e24f5149656e295946e2ab36cd58626fcc2c51c (diff) | |
| download | ghdl-0512b63484398a6220156a989e7bfc6efdc5b038.tar.gz ghdl-0512b63484398a6220156a989e7bfc6efdc5b038.tar.bz2 ghdl-0512b63484398a6220156a989e7bfc6efdc5b038.zip | |
netlists-disp_vhdl: minor rework.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 1458c8cad..94c5398b3 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -1045,13 +1045,13 @@ package body Netlists.Disp_Vhdl is W : constant Width := Get_Width (Get_Output (Inst, 0)); begin if W = 0 then + -- Do not try to slice the input, as it can be a single + -- wire. Disp_Template (" \o0 <= """"", Inst); else Disp_Template (" \o0 <= \i0 ", Inst); if W = 1 then Disp_Template ("(0)", Inst); - elsif W = 0 then - Disp_Template ("(-1 downto 0)", Inst); else Disp_Template ("(\n0 downto 0)", Inst, (0 => W - 1)); end if; |