vhdl: parse and analyze force/release signal assignment statements.

For #1416

21 files changed, 923 insertions, 385 deletions

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index f1eb1b721..32e07a6c5 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -239,90 +239,92 @@ class Iir_Kind:
     Simple_Signal_Assignment_Statement = 224
     Conditional_Signal_Assignment_Statement = 225
     Selected_Waveform_Assignment_Statement = 226
-    Null_Statement = 227
-    Assertion_Statement = 228
-    Report_Statement = 229
-    Wait_Statement = 230
-    Variable_Assignment_Statement = 231
-    Conditional_Variable_Assignment_Statement = 232
-    Return_Statement = 233
-    For_Loop_Statement = 234
-    While_Loop_Statement = 235
-    Next_Statement = 236
-    Exit_Statement = 237
-    Case_Statement = 238
-    Procedure_Call_Statement = 239
-    Break_Statement = 240
-    If_Statement = 241
-    Elsif = 242
-    Character_Literal = 243
-    Simple_Name = 244
-    Selected_Name = 245
-    Operator_Symbol = 246
-    Reference_Name = 247
-    External_Constant_Name = 248
-    External_Signal_Name = 249
-    External_Variable_Name = 250
-    Selected_By_All_Name = 251
-    Parenthesis_Name = 252
-    Package_Pathname = 253
-    Absolute_Pathname = 254
-    Relative_Pathname = 255
-    Pathname_Element = 256
-    Base_Attribute = 257
-    Subtype_Attribute = 258
-    Element_Attribute = 259
-    Across_Attribute = 260
-    Through_Attribute = 261
-    Nature_Reference_Attribute = 262
-    Left_Type_Attribute = 263
-    Right_Type_Attribute = 264
-    High_Type_Attribute = 265
-    Low_Type_Attribute = 266
-    Ascending_Type_Attribute = 267
-    Image_Attribute = 268
-    Value_Attribute = 269
-    Pos_Attribute = 270
-    Val_Attribute = 271
-    Succ_Attribute = 272
-    Pred_Attribute = 273
-    Leftof_Attribute = 274
-    Rightof_Attribute = 275
-    Signal_Slew_Attribute = 276
-    Quantity_Slew_Attribute = 277
-    Ramp_Attribute = 278
-    Zoh_Attribute = 279
-    Ltf_Attribute = 280
-    Ztf_Attribute = 281
-    Dot_Attribute = 282
-    Integ_Attribute = 283
-    Above_Attribute = 284
-    Quantity_Delayed_Attribute = 285
-    Delayed_Attribute = 286
-    Stable_Attribute = 287
-    Quiet_Attribute = 288
-    Transaction_Attribute = 289
-    Event_Attribute = 290
-    Active_Attribute = 291
-    Last_Event_Attribute = 292
-    Last_Active_Attribute = 293
-    Last_Value_Attribute = 294
-    Driving_Attribute = 295
-    Driving_Value_Attribute = 296
-    Behavior_Attribute = 297
-    Structure_Attribute = 298
-    Simple_Name_Attribute = 299
-    Instance_Name_Attribute = 300
-    Path_Name_Attribute = 301
-    Left_Array_Attribute = 302
-    Right_Array_Attribute = 303
-    High_Array_Attribute = 304
-    Low_Array_Attribute = 305
-    Length_Array_Attribute = 306
-    Ascending_Array_Attribute = 307
-    Range_Array_Attribute = 308
-    Reverse_Range_Array_Attribute = 309
-    Attribute_Name = 310
+    Signal_Force_Assignment_Statement = 227
+    Signal_Release_Assignment_Statement = 228
+    Null_Statement = 229
+    Assertion_Statement = 230
+    Report_Statement = 231
+    Wait_Statement = 232
+    Variable_Assignment_Statement = 233
+    Conditional_Variable_Assignment_Statement = 234
+    Return_Statement = 235
+    For_Loop_Statement = 236
+    While_Loop_Statement = 237
+    Next_Statement = 238
+    Exit_Statement = 239
+    Case_Statement = 240
+    Procedure_Call_Statement = 241
+    Break_Statement = 242
+    If_Statement = 243
+    Elsif = 244
+    Character_Literal = 245
+    Simple_Name = 246
+    Selected_Name = 247
+    Operator_Symbol = 248
+    Reference_Name = 249
+    External_Constant_Name = 250
+    External_Signal_Name = 251
+    External_Variable_Name = 252
+    Selected_By_All_Name = 253
+    Parenthesis_Name = 254
+    Package_Pathname = 255
+    Absolute_Pathname = 256
+    Relative_Pathname = 257
+    Pathname_Element = 258
+    Base_Attribute = 259
+    Subtype_Attribute = 260
+    Element_Attribute = 261
+    Across_Attribute = 262
+    Through_Attribute = 263
+    Nature_Reference_Attribute = 264
+    Left_Type_Attribute = 265
+    Right_Type_Attribute = 266
+    High_Type_Attribute = 267
+    Low_Type_Attribute = 268
+    Ascending_Type_Attribute = 269
+    Image_Attribute = 270
+    Value_Attribute = 271
+    Pos_Attribute = 272
+    Val_Attribute = 273
+    Succ_Attribute = 274
+    Pred_Attribute = 275
+    Leftof_Attribute = 276
+    Rightof_Attribute = 277
+    Signal_Slew_Attribute = 278
+    Quantity_Slew_Attribute = 279
+    Ramp_Attribute = 280
+    Zoh_Attribute = 281
+    Ltf_Attribute = 282
+    Ztf_Attribute = 283
+    Dot_Attribute = 284
+    Integ_Attribute = 285
+    Above_Attribute = 286
+    Quantity_Delayed_Attribute = 287
+    Delayed_Attribute = 288
+    Stable_Attribute = 289
+    Quiet_Attribute = 290
+    Transaction_Attribute = 291
+    Event_Attribute = 292
+    Active_Attribute = 293
+    Last_Event_Attribute = 294
+    Last_Active_Attribute = 295
+    Last_Value_Attribute = 296
+    Driving_Attribute = 297
+    Driving_Value_Attribute = 298
+    Behavior_Attribute = 299
+    Structure_Attribute = 300
+    Simple_Name_Attribute = 301
+    Instance_Name_Attribute = 302
+    Path_Name_Attribute = 303
+    Left_Array_Attribute = 304
+    Right_Array_Attribute = 305
+    High_Array_Attribute = 306
+    Low_Array_Attribute = 307
+    Length_Array_Attribute = 308
+    Ascending_Array_Attribute = 309
+    Range_Array_Attribute = 310
+    Reverse_Range_Array_Attribute = 311
+    Attribute_Name = 312
 
 
 class Iir_Kinds:
@@ -682,6 +684,8 @@ class Iir_Kinds:
         Iir_Kind.Simple_Signal_Assignment_Statement,
         Iir_Kind.Conditional_Signal_Assignment_Statement,
         Iir_Kind.Selected_Waveform_Assignment_Statement,
+        Iir_Kind.Signal_Force_Assignment_Statement,
+        Iir_Kind.Signal_Release_Assignment_Statement,
         Iir_Kind.Null_Statement,
         Iir_Kind.Assertion_Statement,
         Iir_Kind.Report_Statement,
@@ -2365,6 +2369,14 @@ Get_Reject_Time_Expression = libghdl.vhdl__nodes__get_reject_time_expression
 
 Set_Reject_Time_Expression = libghdl.vhdl__nodes__set_reject_time_expression
 
+Get_Force_Mode = libghdl.vhdl__nodes__get_force_mode
+
+Set_Force_Mode = libghdl.vhdl__nodes__set_force_mode
+
+Get_Has_Force_Mode = libghdl.vhdl__nodes__get_has_force_mode
+
+Set_Has_Force_Mode = libghdl.vhdl__nodes__set_has_force_mode
+
 Get_Sensitivity_List = libghdl.vhdl__nodes__get_sensitivity_list
 
 Set_Sensitivity_List = libghdl.vhdl__nodes__set_sensitivity_list
diff --git a/python/libghdl/thin/vhdl/nodes_meta.py b/python/libghdl/thin/vhdl/nodes_meta.py
index 352f30ca7..68b9e51a0 100644
--- a/python/libghdl/thin/vhdl/nodes_meta.py
+++ b/python/libghdl/thin/vhdl/nodes_meta.py
@@ -26,27 +26,28 @@ class types:
     Iir_Constraint = 8
     Iir_Delay_Mechanism = 9
     Iir_Flist = 10
-    Iir_Index32 = 11
-    Iir_Int32 = 12
-    Iir_List = 13
-    Iir_Mode = 14
-    Iir_Predefined_Functions = 15
-    Iir_Pure_State = 16
-    Iir_Signal_Kind = 17
-    Iir_Staticness = 18
-    Int32 = 19
-    Int64 = 20
-    Name_Id = 21
-    Number_Base_Type = 22
-    PSL_NFA = 23
-    PSL_Node = 24
-    Scalar_Size = 25
-    Source_File_Entry = 26
-    Source_Ptr = 27
-    String8_Id = 28
-    Time_Stamp_Id = 29
-    Token_Type = 30
-    Tri_State_Type = 31
+    Iir_Force_Mode = 11
+    Iir_Index32 = 12
+    Iir_Int32 = 13
+    Iir_List = 14
+    Iir_Mode = 15
+    Iir_Predefined_Functions = 16
+    Iir_Pure_State = 17
+    Iir_Signal_Kind = 18
+    Iir_Staticness = 19
+    Int32 = 20
+    Int64 = 21
+    Name_Id = 22
+    Number_Base_Type = 23
+    PSL_NFA = 24
+    PSL_Node = 25
+    Scalar_Size = 26
+    Source_File_Entry = 27
+    Source_Ptr = 28
+    String8_Id = 29
+    Time_Stamp_Id = 30
+    Token_Type = 31
+    Tri_State_Type = 32
 
 
 class Attr:
@@ -258,174 +259,176 @@ class fields:
     Guard = 193
     Delay_Mechanism = 194
     Reject_Time_Expression = 195
-    Sensitivity_List = 196
-    Process_Origin = 197
-    Package_Origin = 198
-    Condition_Clause = 199
-    Break_Element = 200
-    Selector_Quantity = 201
-    Break_Quantity = 202
-    Timeout_Clause = 203
-    Postponed_Flag = 204
-    Callees_List = 205
-    Passive_Flag = 206
-    Resolution_Function_Flag = 207
-    Wait_State = 208
-    All_Sensitized_State = 209
-    Seen_Flag = 210
-    Pure_Flag = 211
-    Foreign_Flag = 212
-    Resolved_Flag = 213
-    Signal_Type_Flag = 214
-    Has_Signal_Flag = 215
-    Purity_State = 216
-    Elab_Flag = 217
-    Vendor_Library_Flag = 218
-    Configuration_Mark_Flag = 219
-    Configuration_Done_Flag = 220
-    Index_Constraint_Flag = 221
-    Hide_Implicit_Flag = 222
-    Assertion_Condition = 223
-    Report_Expression = 224
-    Severity_Expression = 225
-    Instantiated_Unit = 226
-    Generic_Map_Aspect_Chain = 227
-    Port_Map_Aspect_Chain = 228
-    Configuration_Name = 229
-    Component_Configuration = 230
-    Configuration_Specification = 231
-    Default_Binding_Indication = 232
-    Default_Configuration_Declaration = 233
-    Expression = 234
-    Conditional_Expression_Chain = 235
-    Allocator_Designated_Type = 236
-    Selected_Waveform_Chain = 237
-    Conditional_Waveform_Chain = 238
-    Guard_Expression = 239
-    Guard_Decl = 240
-    Guard_Sensitivity_List = 241
-    Signal_Attribute_Chain = 242
-    Block_Block_Configuration = 243
-    Package_Header = 244
-    Block_Header = 245
-    Uninstantiated_Package_Name = 246
-    Uninstantiated_Package_Decl = 247
-    Instance_Source_File = 248
-    Generate_Block_Configuration = 249
-    Generate_Statement_Body = 250
-    Alternative_Label = 251
-    Generate_Else_Clause = 252
-    Condition = 253
-    Else_Clause = 254
-    Parameter_Specification = 255
-    Parent = 256
-    Loop_Label = 257
-    Exit_Flag = 258
-    Next_Flag = 259
-    Component_Name = 260
-    Instantiation_List = 261
-    Entity_Aspect = 262
-    Default_Entity_Aspect = 263
-    Binding_Indication = 264
-    Named_Entity = 265
-    Alias_Declaration = 266
-    Referenced_Name = 267
-    Expr_Staticness = 268
-    Scalar_Size = 269
-    Error_Origin = 270
-    Operand = 271
-    Left = 272
-    Right = 273
-    Unit_Name = 274
-    Name = 275
-    Group_Template_Name = 276
-    Name_Staticness = 277
-    Prefix = 278
-    Signature_Prefix = 279
-    External_Pathname = 280
-    Pathname_Suffix = 281
-    Pathname_Expression = 282
-    In_Formal_Flag = 283
-    Slice_Subtype = 284
-    Suffix = 285
-    Index_Subtype = 286
-    Parameter = 287
-    Parameter_2 = 288
-    Parameter_3 = 289
-    Parameter_4 = 290
-    Attr_Chain = 291
-    Signal_Attribute_Declaration = 292
-    Actual_Type = 293
-    Actual_Type_Definition = 294
-    Association_Chain = 295
-    Individual_Association_Chain = 296
-    Subprogram_Association_Chain = 297
-    Aggregate_Info = 298
-    Sub_Aggregate_Info = 299
-    Aggr_Dynamic_Flag = 300
-    Aggr_Min_Length = 301
-    Aggr_Low_Limit = 302
-    Aggr_High_Limit = 303
-    Aggr_Others_Flag = 304
-    Aggr_Named_Flag = 305
-    Aggregate_Expand_Flag = 306
-    Association_Choices_Chain = 307
-    Case_Statement_Alternative_Chain = 308
-    Choice_Staticness = 309
-    Procedure_Call = 310
-    Implementation = 311
-    Parameter_Association_Chain = 312
-    Method_Object = 313
-    Subtype_Type_Mark = 314
-    Subnature_Nature_Mark = 315
-    Type_Conversion_Subtype = 316
-    Type_Mark = 317
-    File_Type_Mark = 318
-    Return_Type_Mark = 319
-    Has_Disconnect_Flag = 320
-    Has_Active_Flag = 321
-    Is_Within_Flag = 322
-    Type_Marks_List = 323
-    Implicit_Alias_Flag = 324
-    Alias_Signature = 325
-    Attribute_Signature = 326
-    Overload_List = 327
-    Simple_Name_Identifier = 328
-    Simple_Name_Subtype = 329
-    Protected_Type_Body = 330
-    Protected_Type_Declaration = 331
-    Use_Flag = 332
-    End_Has_Reserved_Id = 333
-    End_Has_Identifier = 334
-    End_Has_Postponed = 335
-    Has_Label = 336
-    Has_Begin = 337
-    Has_End = 338
-    Has_Is = 339
-    Has_Pure = 340
-    Has_Body = 341
-    Has_Parameter = 342
-    Has_Component = 343
-    Has_Identifier_List = 344
-    Has_Mode = 345
-    Has_Class = 346
-    Has_Delay_Mechanism = 347
-    Suspend_Flag = 348
-    Is_Ref = 349
-    Is_Forward_Ref = 350
-    Psl_Property = 351
-    Psl_Sequence = 352
-    Psl_Declaration = 353
-    Psl_Expression = 354
-    Psl_Boolean = 355
-    PSL_Clock = 356
-    PSL_NFA = 357
-    PSL_Nbr_States = 358
-    PSL_Clock_Sensitivity = 359
-    PSL_EOS_Flag = 360
-    Count_Expression = 361
-    Clock_Expression = 362
-    Default_Clock = 363
+    Force_Mode = 196
+    Has_Force_Mode = 197
+    Sensitivity_List = 198
+    Process_Origin = 199
+    Package_Origin = 200
+    Condition_Clause = 201
+    Break_Element = 202
+    Selector_Quantity = 203
+    Break_Quantity = 204
+    Timeout_Clause = 205
+    Postponed_Flag = 206
+    Callees_List = 207
+    Passive_Flag = 208
+    Resolution_Function_Flag = 209
+    Wait_State = 210
+    All_Sensitized_State = 211
+    Seen_Flag = 212
+    Pure_Flag = 213
+    Foreign_Flag = 214
+    Resolved_Flag = 215
+    Signal_Type_Flag = 216
+    Has_Signal_Flag = 217
+    Purity_State = 218
+    Elab_Flag = 219
+    Vendor_Library_Flag = 220
+    Configuration_Mark_Flag = 221
+    Configuration_Done_Flag = 222
+    Index_Constraint_Flag = 223
+    Hide_Implicit_Flag = 224
+    Assertion_Condition = 225
+    Report_Expression = 226
+    Severity_Expression = 227
+    Instantiated_Unit = 228
+    Generic_Map_Aspect_Chain = 229
+    Port_Map_Aspect_Chain = 230
+    Configuration_Name = 231
+    Component_Configuration = 232
+    Configuration_Specification = 233
+    Default_Binding_Indication = 234
+    Default_Configuration_Declaration = 235
+    Expression = 236
+    Conditional_Expression_Chain = 237
+    Allocator_Designated_Type = 238
+    Selected_Waveform_Chain = 239
+    Conditional_Waveform_Chain = 240
+    Guard_Expression = 241
+    Guard_Decl = 242
+    Guard_Sensitivity_List = 243
+    Signal_Attribute_Chain = 244
+    Block_Block_Configuration = 245
+    Package_Header = 246
+    Block_Header = 247
+    Uninstantiated_Package_Name = 248
+    Uninstantiated_Package_Decl = 249
+    Instance_Source_File = 250
+    Generate_Block_Configuration = 251
+    Generate_Statement_Body = 252
+    Alternative_Label = 253
+    Generate_Else_Clause = 254
+    Condition = 255
+    Else_Clause = 256
+    Parameter_Specification = 257
+    Parent = 258
+    Loop_Label = 259
+    Exit_Flag = 260
+    Next_Flag = 261
+    Component_Name = 262
+    Instantiation_List = 263
+    Entity_Aspect = 264
+    Default_Entity_Aspect = 265
+    Binding_Indication = 266
+    Named_Entity = 267
+    Alias_Declaration = 268
+    Referenced_Name = 269
+    Expr_Staticness = 270
+    Scalar_Size = 271
+    Error_Origin = 272
+    Operand = 273
+    Left = 274
+    Right = 275
+    Unit_Name = 276
+    Name = 277
+    Group_Template_Name = 278
+    Name_Staticness = 279
+    Prefix = 280
+    Signature_Prefix = 281
+    External_Pathname = 282
+    Pathname_Suffix = 283
+    Pathname_Expression = 284
+    In_Formal_Flag = 285
+    Slice_Subtype = 286
+    Suffix = 287
+    Index_Subtype = 288
+    Parameter = 289
+    Parameter_2 = 290
+    Parameter_3 = 291
+    Parameter_4 = 292
+    Attr_Chain = 293
+    Signal_Attribute_Declaration = 294
+    Actual_Type = 295
+    Actual_Type_Definition = 296
+    Association_Chain = 297
+    Individual_Association_Chain = 298
+    Subprogram_Association_Chain = 299
+    Aggregate_Info = 300
+    Sub_Aggregate_Info = 301
+    Aggr_Dynamic_Flag = 302
+    Aggr_Min_Length = 303
+    Aggr_Low_Limit = 304
+    Aggr_High_Limit = 305
+    Aggr_Others_Flag = 306
+    Aggr_Named_Flag = 307
+    Aggregate_Expand_Flag = 308
+    Association_Choices_Chain = 309
+    Case_Statement_Alternative_Chain = 310
+    Choice_Staticness = 311
+    Procedure_Call = 312
+    Implementation = 313
+    Parameter_Association_Chain = 314
+    Method_Object = 315
+    Subtype_Type_Mark = 316
+    Subnature_Nature_Mark = 317
+    Type_Conversion_Subtype = 318
+    Type_Mark = 319
+    File_Type_Mark = 320
+    Return_Type_Mark = 321
+    Has_Disconnect_Flag = 322
+    Has_Active_Flag = 323
+    Is_Within_Flag = 324
+    Type_Marks_List = 325
+    Implicit_Alias_Flag = 326
+    Alias_Signature = 327
+    Attribute_Signature = 328
+    Overload_List = 329
+    Simple_Name_Identifier = 330
+    Simple_Name_Subtype = 331
+    Protected_Type_Body = 332
+    Protected_Type_Declaration = 333
+    Use_Flag = 334
+    End_Has_Reserved_Id = 335
+    End_Has_Identifier = 336
+    End_Has_Postponed = 337
+    Has_Label = 338
+    Has_Begin = 339
+    Has_End = 340
+    Has_Is = 341
+    Has_Pure = 342
+    Has_Body = 343
+    Has_Parameter = 344
+    Has_Component = 345
+    Has_Identifier_List = 346
+    Has_Mode = 347
+    Has_Class = 348
+    Has_Delay_Mechanism = 349
+    Suspend_Flag = 350
+    Is_Ref = 351
+    Is_Forward_Ref = 352
+    Psl_Property = 353
+    Psl_Sequence = 354
+    Psl_Declaration = 355
+    Psl_Expression = 356
+    Psl_Boolean = 357
+    PSL_Clock = 358
+    PSL_NFA = 359
+    PSL_Nbr_States = 360
+    PSL_Clock_Sensitivity = 361
+    PSL_EOS_Flag = 362
+    Count_Expression = 363
+    Clock_Expression = 364
+    Default_Clock = 365
 
 
 Get_Boolean = libghdl.vhdl__nodes_meta__get_boolean
@@ -450,6 +453,8 @@ Get_Iir_Delay_Mechanism = libghdl.vhdl__nodes_meta__get_iir_delay_mechanism
 
 Get_Iir_Flist = libghdl.vhdl__nodes_meta__get_iir_flist
 
+Get_Iir_Force_Mode = libghdl.vhdl__nodes_meta__get_iir_force_mode
+
 Get_Iir_Index32 = libghdl.vhdl__nodes_meta__get_iir_index32
 
 Get_Iir_Int32 = libghdl.vhdl__nodes_meta__get_iir_int32
@@ -1081,6 +1086,12 @@ Has_Delay_Mechanism =\
 Has_Reject_Time_Expression =\
     libghdl.vhdl__nodes_meta__has_reject_time_expression
 
+Has_Force_Mode =\
+    libghdl.vhdl__nodes_meta__has_force_mode
+
+Has_Has_Force_Mode =\
+    libghdl.vhdl__nodes_meta__has_has_force_mode
+
 Has_Sensitivity_List =\
     libghdl.vhdl__nodes_meta__has_sensitivity_list
 
diff --git a/src/ghdldrv/ghdlxml.adb b/src/ghdldrv/ghdlxml.adb
index 46bffd9ea..b135c384c 100644
--- a/src/ghdldrv/ghdlxml.adb
+++ b/src/ghdldrv/ghdlxml.adb
@@ -362,6 +362,9 @@ package body Ghdlxml is
                     (F, Image_Iir_Constraint (Get_Iir_Constraint (N, F)));
                when Type_Iir_Mode =>
                   Put_Field (F, Image_Iir_Mode (Get_Iir_Mode (N, F)));
+               when Type_Iir_Force_Mode =>
+                  Put_Field (F, Image_Iir_Force_Mode
+                               (Get_Iir_Force_Mode (N, F)));
                when Type_Iir_Index32 =>
                   Put_Field (F, Iir_Index32'Image (Get_Iir_Index32 (N, F)));
                when Type_Int64 =>
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 6d918b63a..bf704532a 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -1470,6 +1470,7 @@ package body Trans.Chap2 is
                   | Type_Tri_State_Type
                   | Type_Iir_Pure_State
                   | Type_Iir_Delay_Mechanism
+                  | Type_Iir_Force_Mode
                   | Type_Iir_Predefined_Functions
                   | Type_Direction_Type
                   | Type_Iir_Int32
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index d1bd829cb..dc59757a9 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -1382,6 +1382,7 @@ package body Trans.Chap9 is
                  | Type_Tri_State_Type
                  | Type_Iir_Pure_State
                  | Type_Iir_Delay_Mechanism
+                 | Type_Iir_Force_Mode
                  | Type_Iir_Predefined_Functions
                  | Type_Direction_Type
                  | Type_Iir_Int32
diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb
index fe16b65fd..5c6e22bef 100644
--- a/src/vhdl/translate/trans_analyzes.adb
+++ b/src/vhdl/translate/trans_analyzes.adb
@@ -86,6 +86,9 @@ package body Trans_Analyzes is
                     (Get_Target (Stmt), Extract_Driver_Target'Access);
                end if;
             end;
+         when Iir_Kind_Signal_Force_Assignment_Statement
+            | Iir_Kind_Signal_Release_Assignment_Statement =>
+            null;
          when Iir_Kind_Conditional_Signal_Assignment_Statement =>
             declare
                Cond_Wf : Iir;
diff --git a/src/vhdl/vhdl-disp_tree.adb b/src/vhdl/vhdl-disp_tree.adb
index 06a06d640..031c92e26 100644
--- a/src/vhdl/vhdl-disp_tree.adb
+++ b/src/vhdl/vhdl-disp_tree.adb
@@ -206,6 +206,16 @@ package body Vhdl.Disp_Tree is
       end case;
    end Image_Iir_Delay_Mechanism;
 
+   function Image_Iir_Force_Mode (Mode : Iir_Force_Mode) return String is
+   begin
+      case Mode is
+         when Iir_Force_In =>
+            return "in";
+         when Iir_Force_Out =>
+            return "out";
+      end case;
+   end Image_Iir_Force_Mode;
+
    function Image_Iir_Mode (Mode : Iir_Mode) return String is
    begin
       case Mode is
@@ -572,6 +582,8 @@ package body Vhdl.Disp_Tree is
                when Type_Iir_Delay_Mechanism =>
                   Log_Line (Image_Iir_Delay_Mechanism
                               (Get_Iir_Delay_Mechanism (N, F)));
+               when Type_Iir_Force_Mode =>
+                  Log_Line (Image_Iir_Force_Mode (Get_Iir_Force_Mode (N, F)));
                when Type_Iir_Predefined_Functions =>
                   Log_Line (Image_Iir_Predefined_Functions
                               (Get_Iir_Predefined_Functions (N, F)));
diff --git a/src/vhdl/vhdl-disp_tree.ads b/src/vhdl/vhdl-disp_tree.ads
index 3dcf8bd1b..16652feee 100644
--- a/src/vhdl/vhdl-disp_tree.ads
+++ b/src/vhdl/vhdl-disp_tree.ads
@@ -35,6 +35,7 @@ package Vhdl.Disp_Tree is
    function Image_Iir_Delay_Mechanism (Mech : Iir_Delay_Mechanism)
                                       return String;
    function Image_Iir_Mode (Mode : Iir_Mode) return String;
+   function Image_Iir_Force_Mode (Mode : Iir_Force_Mode) return String;
    function Image_Iir_Signal_Kind (Kind : Iir_Signal_Kind) return String;
    function Image_Iir_Pure_State (State : Iir_Pure_State) return String;
    function Image_Iir_All_Sensitized (Sig : Iir_All_Sensitized)
diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb
index 35689c11a..09730e936 100644
--- a/src/vhdl/vhdl-elocations.adb
+++ b/src/vhdl/vhdl-elocations.adb
@@ -369,6 +369,8 @@ package body Vhdl.Elocations is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads
index 700a3d7ca..a4eefba2f 100644
--- a/src/vhdl/vhdl-elocations.ads
+++ b/src/vhdl/vhdl-elocations.ads
@@ -409,6 +409,9 @@ package Vhdl.Elocations is
    --
    --   Get/Set_Start_Location (Field1)
 
+   -- Iir_Kind_Signal_Force_Assignment_Statement (None)
+   -- Iir_Kind_Signal_Release_Assignment_Statement (None)
+
    -- Iir_Kind_Sensitized_Process_Statement (L4)
    -- Iir_Kind_Process_Statement (L4)
    --
diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb
index 9806595ac..52ab0815d 100644
--- a/src/vhdl/vhdl-errors.adb
+++ b/src/vhdl/vhdl-errors.adb
@@ -811,6 +811,10 @@ package body Vhdl.Errors is
          when Iir_Kind_Selected_Waveform_Assignment_Statement =>
             return Disp_Label
               (Node, "selected waveform assignment statement");
+         when Iir_Kind_Signal_Force_Assignment_Statement =>
+            return Disp_Label (Node, "signal force assignment");
+         when Iir_Kind_Signal_Release_Assignment_Statement =>
+            return Disp_Label (Node, "signal release assignment");
          when Iir_Kind_Variable_Assignment_Statement =>
             return Disp_Label (Node, "variable assignment statement");
          when Iir_Kind_Conditional_Variable_Assignment_Statement =>
diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb
index 4891f57a8..ea5652c99 100644
--- a/src/vhdl/vhdl-nodes.adb
+++ b/src/vhdl/vhdl-nodes.adb
@@ -939,6 +939,11 @@ package body Vhdl.Nodes is
    function Iir_Delay_Mechanism_To_Boolean is new Ada.Unchecked_Conversion
      (Source => Iir_Delay_Mechanism, Target => Boolean);
 
+   function Boolean_To_Iir_Force_Mode is new Ada.Unchecked_Conversion
+     (Source => Boolean, Target => Iir_Force_Mode);
+   function Iir_Force_Mode_To_Boolean is new Ada.Unchecked_Conversion
+     (Source => Iir_Force_Mode, Target => Boolean);
+
    function Boolean_To_Iir_Signal_Kind is new Ada.Unchecked_Conversion
      (Source => Boolean, Target => Iir_Signal_Kind);
    function Iir_Signal_Kind_To_Boolean is new Ada.Unchecked_Conversion
@@ -1150,6 +1155,8 @@ package body Vhdl.Nodes is
            | Iir_Kind_Simultaneous_Elsif
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -4528,6 +4535,38 @@ package body Vhdl.Nodes is
       Set_Field4 (Target, Expr);
    end Set_Reject_Time_Expression;
 
+   function Get_Force_Mode (Stmt : Iir) return Iir_Force_Mode is
+   begin
+      pragma Assert (Stmt /= Null_Iir);
+      pragma Assert (Has_Force_Mode (Get_Kind (Stmt)),
+                     "no field Force_Mode");
+      return Boolean_To_Iir_Force_Mode (Get_Flag1 (Stmt));
+   end Get_Force_Mode;
+
+   procedure Set_Force_Mode (Stmt : Iir; Mode : Iir_Force_Mode) is
+   begin
+      pragma Assert (Stmt /= Null_Iir);
+      pragma Assert (Has_Force_Mode (Get_Kind (Stmt)),
+                     "no field Force_Mode");
+      Set_Flag1 (Stmt, Iir_Force_Mode_To_Boolean (Mode));
+   end Set_Force_Mode;
+
+   function Get_Has_Force_Mode (Stmt : Iir) return Boolean is
+   begin
+      pragma Assert (Stmt /= Null_Iir);
+      pragma Assert (Has_Has_Force_Mode (Get_Kind (Stmt)),
+                     "no field Has_Force_Mode");
+      return Get_Flag2 (Stmt);
+   end Get_Has_Force_Mode;
+
+   procedure Set_Has_Force_Mode (Stmt : Iir; Flag : Boolean) is
+   begin
+      pragma Assert (Stmt /= Null_Iir);
+      pragma Assert (Has_Has_Force_Mode (Get_Kind (Stmt)),
+                     "no field Has_Force_Mode");
+      Set_Flag2 (Stmt, Flag);
+   end Set_Has_Force_Mode;
+
    function Get_Sensitivity_List (Wait : Iir) return Iir_List is
    begin
       pragma Assert (Wait /= Null_Iir);
diff --git a/src/vhdl/vhdl-nodes.adb.in b/src/vhdl/vhdl-nodes.adb.in
index 5c77f9fef..e35ed1832 100644
--- a/src/vhdl/vhdl-nodes.adb.in
+++ b/src/vhdl/vhdl-nodes.adb.in
@@ -939,6 +939,11 @@ package body Vhdl.Nodes is
    function Iir_Delay_Mechanism_To_Boolean is new Ada.Unchecked_Conversion
      (Source => Iir_Delay_Mechanism, Target => Boolean);
 
+   function Boolean_To_Iir_Force_Mode is new Ada.Unchecked_Conversion
+     (Source => Boolean, Target => Iir_Force_Mode);
+   function Iir_Force_Mode_To_Boolean is new Ada.Unchecked_Conversion
+     (Source => Iir_Force_Mode, Target => Boolean);
+
    function Boolean_To_Iir_Signal_Kind is new Ada.Unchecked_Conversion
      (Source => Boolean, Target => Iir_Signal_Kind);
    function Iir_Signal_Kind_To_Boolean is new Ada.Unchecked_Conversion
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 88e27434d..adf3b6f59 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -3786,6 +3786,32 @@ package Vhdl.Nodes is
    --
    --   Get/Set_Is_Ref (Flag12)
 
+   -- Iir_Kind_Signal_Force_Assignment_Statement (Short)
+   -- Iir_Kind_Signal_Release_Assignment_Statement (Short)
+   --
+   --   Get/Set_Parent (Field0)
+   --
+   --   Get/Set_Target (Field1)
+   --
+   --   Get/Set_Chain (Field2)
+   --
+   --   Get/Set_Label (Field3)
+   --   Get/Set_Identifier (Alias Field3)
+   --
+   -- Only for Iir_Kind_Signal_Force_Assignment_Statement:
+   --   Get/Set_Expression (Field5)
+   --
+   --   Get/Set_Force_Mode (Flag1)
+   --
+   --   Get/Set_Visible_Flag (Flag4)
+   --
+   --  True if the target of the assignment is guarded
+   --   Get/Set_Guarded_Target_State (State1)
+   --
+   --   Get/Set_Is_Ref (Flag12)
+   --
+   --   Get/Set_Has_Force_Mode (Flag2)
+
    -- Iir_Kind_Simple_Signal_Assignment_Statement (Short)
    -- Iir_Kind_Conditional_Signal_Assignment_Statement (Short)
    -- Iir_Kind_Selected_Waveform_Assignment_Statement (Medium)
@@ -4999,6 +5025,8 @@ package Vhdl.Nodes is
       Iir_Kind_Simple_Signal_Assignment_Statement,
       Iir_Kind_Conditional_Signal_Assignment_Statement,
       Iir_Kind_Selected_Waveform_Assignment_Statement,
+      Iir_Kind_Signal_Force_Assignment_Statement,
+      Iir_Kind_Signal_Release_Assignment_Statement,
       Iir_Kind_Null_Statement,
       Iir_Kind_Assertion_Statement,
       Iir_Kind_Report_Statement,
@@ -5125,6 +5153,12 @@ package Vhdl.Nodes is
       Iir_Transport_Delay
      );
 
+   type Iir_Force_Mode is
+     (
+      Iir_Force_In,
+      Iir_Force_Out
+     );
+
    --  LRM93 2.7 (conformance rules).
    --  To keep this simple, the layout is stored as a bit-string.
    --  Fields are:
@@ -6716,6 +6750,8 @@ package Vhdl.Nodes is
      Iir_Kind_Simple_Signal_Assignment_Statement ..
    --Iir_Kind_Conditional_Signal_Assignment_Statement
    --Iir_Kind_Selected_Waveform_Assignment_Statement
+   --Iir_Kind_Signal_Force_Assignment_Statement
+   --Iir_Kind_Signal_Release_Assignment_Statement
    --Iir_Kind_Null_Statement
    --Iir_Kind_Assertion_Statement
    --Iir_Kind_Report_Statement
@@ -8176,6 +8212,14 @@ package Vhdl.Nodes is
    function Get_Reject_Time_Expression (Target : Iir) return Iir;
    procedure Set_Reject_Time_Expression (Target : Iir; Expr : Iir);
 
+   --  Field: Flag1 (uc)
+   function Get_Force_Mode (Stmt : Iir) return Iir_Force_Mode;
+   procedure Set_Force_Mode (Stmt : Iir; Mode : Iir_Force_Mode);
+
+   --  Field: Flag2
+   function Get_Has_Force_Mode (Stmt : Iir) return Boolean;
+   procedure Set_Has_Force_Mode (Stmt : Iir; Flag : Boolean);
+
    --  The Is_Ref flag is set for extracted sensitivity lists.
    --  Field: Field6 Of_Maybe_Ref (uc)
    function Get_Sensitivity_List (Wait : Iir) return Iir_List;
diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb
index b9a4a562c..020b1c6a8 100644
--- a/src/vhdl/vhdl-nodes_meta.adb
+++ b/src/vhdl/vhdl-nodes_meta.adb
@@ -215,6 +215,8 @@ package body Vhdl.Nodes_Meta is
       Field_Guard => Type_Iir,
       Field_Delay_Mechanism => Type_Iir_Delay_Mechanism,
       Field_Reject_Time_Expression => Type_Iir,
+      Field_Force_Mode => Type_Iir_Force_Mode,
+      Field_Has_Force_Mode => Type_Boolean,
       Field_Sensitivity_List => Type_Iir_List,
       Field_Process_Origin => Type_Iir,
       Field_Package_Origin => Type_Iir,
@@ -785,6 +787,10 @@ package body Vhdl.Nodes_Meta is
             return "delay_mechanism";
          when Field_Reject_Time_Expression =>
             return "reject_time_expression";
+         when Field_Force_Mode =>
+            return "force_mode";
+         when Field_Has_Force_Mode =>
+            return "has_force_mode";
          when Field_Sensitivity_List =>
             return "sensitivity_list";
          when Field_Process_Origin =>
@@ -1581,6 +1587,10 @@ package body Vhdl.Nodes_Meta is
             return "conditional_signal_assignment_statement";
          when Iir_Kind_Selected_Waveform_Assignment_Statement =>
             return "selected_waveform_assignment_statement";
+         when Iir_Kind_Signal_Force_Assignment_Statement =>
+            return "signal_force_assignment_statement";
+         when Iir_Kind_Signal_Release_Assignment_Statement =>
+            return "signal_release_assignment_statement";
          when Iir_Kind_Null_Statement =>
             return "null_statement";
          when Iir_Kind_Assertion_Statement =>
@@ -2147,6 +2157,10 @@ package body Vhdl.Nodes_Meta is
             return Attr_None;
          when Field_Reject_Time_Expression =>
             return Attr_None;
+         when Field_Force_Mode =>
+            return Attr_None;
+         when Field_Has_Force_Mode =>
+            return Attr_None;
          when Field_Sensitivity_List =>
             return Attr_Of_Maybe_Ref;
          when Field_Process_Origin =>
@@ -4515,6 +4529,27 @@ package body Vhdl.Nodes_Meta is
       Field_Reject_Time_Expression,
       Field_Expression,
       Field_Selected_Waveform_Chain,
+      --  Iir_Kind_Signal_Force_Assignment_Statement
+      Field_Label,
+      Field_Force_Mode,
+      Field_Is_Ref,
+      Field_Has_Force_Mode,
+      Field_Visible_Flag,
+      Field_Guarded_Target_State,
+      Field_Parent,
+      Field_Target,
+      Field_Chain,
+      Field_Expression,
+      --  Iir_Kind_Signal_Release_Assignment_Statement
+      Field_Label,
+      Field_Force_Mode,
+      Field_Is_Ref,
+      Field_Has_Force_Mode,
+      Field_Visible_Flag,
+      Field_Guarded_Target_State,
+      Field_Parent,
+      Field_Target,
+      Field_Chain,
       --  Iir_Kind_Null_Statement
       Field_Label,
       Field_Visible_Flag,
@@ -5359,90 +5394,92 @@ package body Vhdl.Nodes_Meta is
       Iir_Kind_Simple_Signal_Assignment_Statement => 1776,
       Iir_Kind_Conditional_Signal_Assignment_Statement => 1787,
       Iir_Kind_Selected_Waveform_Assignment_Statement => 1799,
-      Iir_Kind_Null_Statement => 1803,
-      Iir_Kind_Assertion_Statement => 1810,
-      Iir_Kind_Report_Statement => 1816,
-      Iir_Kind_Wait_Statement => 1824,
-      Iir_Kind_Variable_Assignment_Statement => 1831,
-      Iir_Kind_Conditional_Variable_Assignment_Statement => 1838,
-      Iir_Kind_Return_Statement => 1844,
-      Iir_Kind_For_Loop_Statement => 1855,
-      Iir_Kind_While_Loop_Statement => 1866,
-      Iir_Kind_Next_Statement => 1873,
-      Iir_Kind_Exit_Statement => 1880,
-      Iir_Kind_Case_Statement => 1888,
-      Iir_Kind_Procedure_Call_Statement => 1894,
-      Iir_Kind_Break_Statement => 1901,
-      Iir_Kind_If_Statement => 1911,
-      Iir_Kind_Elsif => 1917,
-      Iir_Kind_Character_Literal => 1925,
-      Iir_Kind_Simple_Name => 1933,
-      Iir_Kind_Selected_Name => 1942,
-      Iir_Kind_Operator_Symbol => 1948,
-      Iir_Kind_Reference_Name => 1953,
-      Iir_Kind_External_Constant_Name => 1962,
-      Iir_Kind_External_Signal_Name => 1971,
-      Iir_Kind_External_Variable_Name => 1981,
-      Iir_Kind_Selected_By_All_Name => 1987,
-      Iir_Kind_Parenthesis_Name => 1992,
-      Iir_Kind_Package_Pathname => 1996,
-      Iir_Kind_Absolute_Pathname => 1997,
-      Iir_Kind_Relative_Pathname => 1998,
-      Iir_Kind_Pathname_Element => 2003,
-      Iir_Kind_Base_Attribute => 2005,
-      Iir_Kind_Subtype_Attribute => 2010,
-      Iir_Kind_Element_Attribute => 2015,
-      Iir_Kind_Across_Attribute => 2020,
-      Iir_Kind_Through_Attribute => 2025,
-      Iir_Kind_Nature_Reference_Attribute => 2029,
-      Iir_Kind_Left_Type_Attribute => 2034,
-      Iir_Kind_Right_Type_Attribute => 2039,
-      Iir_Kind_High_Type_Attribute => 2044,
-      Iir_Kind_Low_Type_Attribute => 2049,
-      Iir_Kind_Ascending_Type_Attribute => 2054,
-      Iir_Kind_Image_Attribute => 2060,
-      Iir_Kind_Value_Attribute => 2066,
-      Iir_Kind_Pos_Attribute => 2072,
-      Iir_Kind_Val_Attribute => 2078,
-      Iir_Kind_Succ_Attribute => 2084,
-      Iir_Kind_Pred_Attribute => 2090,
-      Iir_Kind_Leftof_Attribute => 2096,
-      Iir_Kind_Rightof_Attribute => 2102,
-      Iir_Kind_Signal_Slew_Attribute => 2110,
-      Iir_Kind_Quantity_Slew_Attribute => 2118,
-      Iir_Kind_Ramp_Attribute => 2126,
-      Iir_Kind_Zoh_Attribute => 2134,
-      Iir_Kind_Ltf_Attribute => 2142,
-      Iir_Kind_Ztf_Attribute => 2152,
-      Iir_Kind_Dot_Attribute => 2159,
-      Iir_Kind_Integ_Attribute => 2166,
-      Iir_Kind_Above_Attribute => 2174,
-      Iir_Kind_Quantity_Delayed_Attribute => 2182,
-      Iir_Kind_Delayed_Attribute => 2191,
-      Iir_Kind_Stable_Attribute => 2200,
-      Iir_Kind_Quiet_Attribute => 2209,
-      Iir_Kind_Transaction_Attribute => 2218,
-      Iir_Kind_Event_Attribute => 2222,
-      Iir_Kind_Active_Attribute => 2226,
-      Iir_Kind_Last_Event_Attribute => 2230,
-      Iir_Kind_Last_Active_Attribute => 2234,
-      Iir_Kind_Last_Value_Attribute => 2238,
-      Iir_Kind_Driving_Attribute => 2242,
-      Iir_Kind_Driving_Value_Attribute => 2246,
-      Iir_Kind_Behavior_Attribute => 2246,
-      Iir_Kind_Structure_Attribute => 2246,
-      Iir_Kind_Simple_Name_Attribute => 2253,
-      Iir_Kind_Instance_Name_Attribute => 2258,
-      Iir_Kind_Path_Name_Attribute => 2263,
-      Iir_Kind_Left_Array_Attribute => 2270,
-      Iir_Kind_Right_Array_Attribute => 2277,
-      Iir_Kind_High_Array_Attribute => 2284,
-      Iir_Kind_Low_Array_Attribute => 2291,
-      Iir_Kind_Length_Array_Attribute => 2298,
-      Iir_Kind_Ascending_Array_Attribute => 2305,
-      Iir_Kind_Range_Array_Attribute => 2312,
-      Iir_Kind_Reverse_Range_Array_Attribute => 2319,
-      Iir_Kind_Attribute_Name => 2328
+      Iir_Kind_Signal_Force_Assignment_Statement => 1809,
+      Iir_Kind_Signal_Release_Assignment_Statement => 1818,
+      Iir_Kind_Null_Statement => 1822,
+      Iir_Kind_Assertion_Statement => 1829,
+      Iir_Kind_Report_Statement => 1835,
+      Iir_Kind_Wait_Statement => 1843,
+      Iir_Kind_Variable_Assignment_Statement => 1850,
+      Iir_Kind_Conditional_Variable_Assignment_Statement => 1857,
+      Iir_Kind_Return_Statement => 1863,
+      Iir_Kind_For_Loop_Statement => 1874,
+      Iir_Kind_While_Loop_Statement => 1885,
+      Iir_Kind_Next_Statement => 1892,
+      Iir_Kind_Exit_Statement => 1899,
+      Iir_Kind_Case_Statement => 1907,
+      Iir_Kind_Procedure_Call_Statement => 1913,
+      Iir_Kind_Break_Statement => 1920,
+      Iir_Kind_If_Statement => 1930,
+      Iir_Kind_Elsif => 1936,
+      Iir_Kind_Character_Literal => 1944,
+      Iir_Kind_Simple_Name => 1952,
+      Iir_Kind_Selected_Name => 1961,
+      Iir_Kind_Operator_Symbol => 1967,
+      Iir_Kind_Reference_Name => 1972,
+      Iir_Kind_External_Constant_Name => 1981,
+      Iir_Kind_External_Signal_Name => 1990,
+      Iir_Kind_External_Variable_Name => 2000,
+      Iir_Kind_Selected_By_All_Name => 2006,
+      Iir_Kind_Parenthesis_Name => 2011,
+      Iir_Kind_Package_Pathname => 2015,
+      Iir_Kind_Absolute_Pathname => 2016,
+      Iir_Kind_Relative_Pathname => 2017,
+      Iir_Kind_Pathname_Element => 2022,
+      Iir_Kind_Base_Attribute => 2024,
+      Iir_Kind_Subtype_Attribute => 2029,
+      Iir_Kind_Element_Attribute => 2034,
+      Iir_Kind_Across_Attribute => 2039,
+      Iir_Kind_Through_Attribute => 2044,
+      Iir_Kind_Nature_Reference_Attribute => 2048,
+      Iir_Kind_Left_Type_Attribute => 2053,
+      Iir_Kind_Right_Type_Attribute => 2058,
+      Iir_Kind_High_Type_Attribute => 2063,
+      Iir_Kind_Low_Type_Attribute => 2068,
+      Iir_Kind_Ascending_Type_Attribute => 2073,
+      Iir_Kind_Image_Attribute => 2079,
+      Iir_Kind_Value_Attribute => 2085,
+      Iir_Kind_Pos_Attribute => 2091,
+      Iir_Kind_Val_Attribute => 2097,
+      Iir_Kind_Succ_Attribute => 2103,
+      Iir_Kind_Pred_Attribute => 2109,
+      Iir_Kind_Leftof_Attribute => 2115,
+      Iir_Kind_Rightof_Attribute => 2121,
+      Iir_Kind_Signal_Slew_Attribute => 2129,
+      Iir_Kind_Quantity_Slew_Attribute => 2137,
+      Iir_Kind_Ramp_Attribute => 2145,
+      Iir_Kind_Zoh_Attribute => 2153,
+      Iir_Kind_Ltf_Attribute => 2161,
+      Iir_Kind_Ztf_Attribute => 2171,
+      Iir_Kind_Dot_Attribute => 2178,
+      Iir_Kind_Integ_Attribute => 2185,
+      Iir_Kind_Above_Attribute => 2193,
+      Iir_Kind_Quantity_Delayed_Attribute => 2201,
+      Iir_Kind_Delayed_Attribute => 2210,
+      Iir_Kind_Stable_Attribute => 2219,
+      Iir_Kind_Quiet_Attribute => 2228,
+      Iir_Kind_Transaction_Attribute => 2237,
+      Iir_Kind_Event_Attribute => 2241,
+      Iir_Kind_Active_Attribute => 2245,
+      Iir_Kind_Last_Event_Attribute => 2249,
+      Iir_Kind_Last_Active_Attribute => 2253,
+      Iir_Kind_Last_Value_Attribute => 2257,
+      Iir_Kind_Driving_Attribute => 2261,
+      Iir_Kind_Driving_Value_Attribute => 2265,
+      Iir_Kind_Behavior_Attribute => 2265,
+      Iir_Kind_Structure_Attribute => 2265,
+      Iir_Kind_Simple_Name_Attribute => 2272,
+      Iir_Kind_Instance_Name_Attribute => 2277,
+      Iir_Kind_Path_Name_Attribute => 2282,
+      Iir_Kind_Left_Array_Attribute => 2289,
+      Iir_Kind_Right_Array_Attribute => 2296,
+      Iir_Kind_High_Array_Attribute => 2303,
+      Iir_Kind_Low_Array_Attribute => 2310,
+      Iir_Kind_Length_Array_Attribute => 2317,
+      Iir_Kind_Ascending_Array_Attribute => 2324,
+      Iir_Kind_Range_Array_Attribute => 2331,
+      Iir_Kind_Reverse_Range_Array_Attribute => 2338,
+      Iir_Kind_Attribute_Name => 2347
      );
 
    function Get_Fields_First (K : Iir_Kind) return Fields_Index is
@@ -5517,6 +5554,8 @@ package body Vhdl.Nodes_Meta is
             return Get_Only_Characters_Flag (N);
          when Field_Is_Character_Type =>
             return Get_Is_Character_Type (N);
+         when Field_Has_Force_Mode =>
+            return Get_Has_Force_Mode (N);
          when Field_Postponed_Flag =>
             return Get_Postponed_Flag (N);
          when Field_Passive_Flag =>
@@ -5659,6 +5698,8 @@ package body Vhdl.Nodes_Meta is
             Set_Only_Characters_Flag (N, V);
          when Field_Is_Character_Type =>
             Set_Is_Character_Type (N, V);
+         when Field_Has_Force_Mode =>
+            Set_Has_Force_Mode (N, V);
          when Field_Postponed_Flag =>
             Set_Postponed_Flag (N, V);
          when Field_Passive_Flag =>
@@ -6932,6 +6973,30 @@ package body Vhdl.Nodes_Meta is
       end case;
    end Set_Iir_Flist;
 
+   function Get_Iir_Force_Mode
+      (N : Iir; F : Fields_Enum) return Iir_Force_Mode is
+   begin
+      pragma Assert (Fields_Type (F) = Type_Iir_Force_Mode);
+      case F is
+         when Field_Force_Mode =>
+            return Get_Force_Mode (N);
+         when others =>
+            raise Internal_Error;
+      end case;
+   end Get_Iir_Force_Mode;
+
+   procedure Set_Iir_Force_Mode
+      (N : Iir; F : Fields_Enum; V: Iir_Force_Mode) is
+   begin
+      pragma Assert (Fields_Type (F) = Type_Iir_Force_Mode);
+      case F is
+         when Field_Force_Mode =>
+            Set_Force_Mode (N, V);
+         when others =>
+            raise Internal_Error;
+      end case;
+   end Set_Iir_Force_Mode;
+
    function Get_Iir_Index32
       (N : Iir; F : Fields_Enum) return Iir_Index32 is
    begin
@@ -7678,7 +7743,9 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Concurrent_Selected_Signal_Assignment
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
-           | Iir_Kind_Selected_Waveform_Assignment_Statement =>
+           | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement =>
             return True;
          when others =>
             return False;
@@ -8385,6 +8452,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -9257,6 +9326,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -9314,6 +9385,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -9415,6 +9488,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -9924,6 +9999,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Variable_Assignment_Statement
            | Iir_Kind_Conditional_Variable_Assignment_Statement =>
             return True;
@@ -9986,6 +10063,28 @@ package body Vhdl.Nodes_Meta is
       end case;
    end Has_Reject_Time_Expression;
 
+   function Has_Force_Mode (K : Iir_Kind) return Boolean is
+   begin
+      case K is
+         when Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement =>
+            return True;
+         when others =>
+            return False;
+      end case;
+   end Has_Force_Mode;
+
+   function Has_Has_Force_Mode (K : Iir_Kind) return Boolean is
+   begin
+      case K is
+         when Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement =>
+            return True;
+         when others =>
+            return False;
+      end case;
+   end Has_Has_Force_Mode;
+
    function Has_Sensitivity_List (K : Iir_Kind) return Boolean is
    begin
       case K is
@@ -10423,6 +10522,7 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Case_Generate_Statement
            | Iir_Kind_Simultaneous_Case_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
            | Iir_Kind_Variable_Assignment_Statement
            | Iir_Kind_Return_Statement
            | Iir_Kind_Case_Statement =>
@@ -10722,6 +10822,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
@@ -12252,6 +12354,8 @@ package body Vhdl.Nodes_Meta is
            | Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Wait_Statement
            | Iir_Kind_Variable_Assignment_Statement
            | Iir_Kind_Conditional_Variable_Assignment_Statement
diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads
index 1b5a19269..b2547ef20 100644
--- a/src/vhdl/vhdl-nodes_meta.ads
+++ b/src/vhdl/vhdl-nodes_meta.ads
@@ -36,6 +36,7 @@ package Vhdl.Nodes_Meta is
       Type_Iir_Constraint,
       Type_Iir_Delay_Mechanism,
       Type_Iir_Flist,
+      Type_Iir_Force_Mode,
       Type_Iir_Index32,
       Type_Iir_Int32,
       Type_Iir_List,
@@ -258,6 +259,8 @@ package Vhdl.Nodes_Meta is
       Field_Guard,
       Field_Delay_Mechanism,
       Field_Reject_Time_Expression,
+      Field_Force_Mode,
+      Field_Has_Force_Mode,
       Field_Sensitivity_List,
       Field_Process_Origin,
       Field_Package_Origin,
@@ -527,6 +530,11 @@ package Vhdl.Nodes_Meta is
    procedure Set_Iir_Flist
       (N : Iir; F : Fields_Enum; V: Iir_Flist);
 
+   function Get_Iir_Force_Mode
+      (N : Iir; F : Fields_Enum) return Iir_Force_Mode;
+   procedure Set_Iir_Force_Mode
+      (N : Iir; F : Fields_Enum; V: Iir_Force_Mode);
+
    function Get_Iir_Index32
       (N : Iir; F : Fields_Enum) return Iir_Index32;
    procedure Set_Iir_Index32
@@ -833,6 +841,8 @@ package Vhdl.Nodes_Meta is
    function Has_Guard (K : Iir_Kind) return Boolean;
    function Has_Delay_Mechanism (K : Iir_Kind) return Boolean;
    function Has_Reject_Time_Expression (K : Iir_Kind) return Boolean;
+   function Has_Force_Mode (K : Iir_Kind) return Boolean;
+   function Has_Has_Force_Mode (K : Iir_Kind) return Boolean;
    function Has_Sensitivity_List (K : Iir_Kind) return Boolean;
    function Has_Process_Origin (K : Iir_Kind) return Boolean;
    function Has_Package_Origin (K : Iir_Kind) return Boolean;
diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb
index 613e2c6b1..79b67cc13 100644
--- a/src/vhdl/vhdl-nodes_walk.adb
+++ b/src/vhdl/vhdl-nodes_walk.adb
@@ -63,6 +63,8 @@ package body Vhdl.Nodes_Walk is
          when Iir_Kind_Simple_Signal_Assignment_Statement
            | Iir_Kind_Conditional_Signal_Assignment_Statement
            | Iir_Kind_Selected_Waveform_Assignment_Statement
+           | Iir_Kind_Signal_Force_Assignment_Statement
+           | Iir_Kind_Signal_Release_Assignment_Statement
            | Iir_Kind_Null_Statement
            | Iir_Kind_Assertion_Statement
            | Iir_Kind_Report_Statement
diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb
index 820594579..7ac389a13 100644
--- a/src/vhdl/vhdl-parse.adb
+++ b/src/vhdl/vhdl-parse.adb
@@ -7250,31 +7250,27 @@ package body Vhdl.Parse is
       return Decl;
    end Parse_Parameter_Specification;
 
-   --  precond:  '<='
+   --  precond:  delay_mechanism or waveform
    --  postcond: next token
    --
    --  [ LRM93 8.4 ]
    --  signal_assignment_statement ::=
-   --      [ label : ] target <= [ delay_mechanism ] waveform ;
+   --    [ label : ] target <= [ delay_mechanism ] waveform ;
    --
    --  [ LRM08 10.5 Signal assignment statement ]
-   --  signal_assignement_statement ::=
-   --      [ label : ] simple_signal_assignement
-   --    | [ label : ] conditional_signal_assignement
-   --    | [ label : ] selected_signal_assignement (TODO)
-   function Parse_Signal_Assignment_Statement (Target : Iir) return Iir
+   --  simple_waveform_assignment ::=
+   --    target <= [ delay_mechanism ] waveform ;
+   function Parse_Signal_Waveform_Assignment
+     (Target : Iir; Loc : Location_Type) return Iir
    is
       Stmt : Iir;
       N_Stmt : Iir;
       Wave_Chain : Iir;
    begin
       Stmt := Create_Iir (Iir_Kind_Simple_Signal_Assignment_Statement);
-      Set_Location (Stmt);
+      Set_Location (Stmt, Loc);
       Set_Target (Stmt, Target);
 
-      --  Skip '<='.
-      Scan;
-
       Parse_Delay_Mechanism (Stmt);
 
       Wave_Chain := Parse_Conditional_Waveforms;
@@ -7308,6 +7304,109 @@ package body Vhdl.Parse is
       end if;
 
       return Stmt;
+   end Parse_Signal_Waveform_Assignment;
+
+   --  precond:  -
+   --  postcond: next token
+   --
+   --  [ LRM08 10.5.2 Simple signal assignments ]
+   --  force_mode ::= IN | OUT
+   procedure Parse_Force_Mode_Opt (Stmt : Iir) is
+   begin
+      case Current_Token is
+         when Tok_In =>
+            Set_Force_Mode (Stmt, Iir_Force_In);
+            Set_Has_Force_Mode (Stmt, True);
+         when Tok_Out =>
+            Set_Force_Mode (Stmt, Iir_Force_Out);
+            Set_Has_Force_Mode (Stmt, True);
+         when others =>
+            null;
+      end case;
+   end Parse_Force_Mode_Opt;
+
+   --  precond:  'force'
+   --  postcond: next token
+   --
+   --  [ LRM08 10.5 Signal assignment statement ]
+   --  simple_force_assignment ::=
+   --    target <= FORCE [ force_mode ] expression ;
+   function Parse_Signal_Force_Assignment
+     (Target : Iir; Loc : Location_Type) return Iir
+   is
+      Stmt : Iir;
+   begin
+      Stmt := Create_Iir (Iir_Kind_Signal_Force_Assignment_Statement);
+      Set_Location (Stmt, Loc);
+      Set_Target (Stmt, Target);
+
+      --  Skip 'force'.
+      Scan;
+
+      Parse_Force_Mode_Opt (Stmt);
+
+      Set_Expression (Stmt, Parse_Expression);
+
+      return Stmt;
+   end Parse_Signal_Force_Assignment;
+
+   --  precond:  'release'
+   --  postcond: next token
+   --
+   --  [ LRM08 10.5 Signal assignment statement ]
+   --  simple_release_assignment ::=
+   --    target <= RELEASE [ force_mode ] expression ;
+   function Parse_Signal_Release_Assignment
+     (Target : Iir; Loc : Location_Type) return Iir
+   is
+      Stmt : Iir;
+   begin
+      Stmt := Create_Iir (Iir_Kind_Signal_Release_Assignment_Statement);
+      Set_Location (Stmt, Loc);
+      Set_Target (Stmt, Target);
+
+      --  Skip 'release'.
+      Scan;
+
+      Parse_Force_Mode_Opt (Stmt);
+
+      return Stmt;
+   end Parse_Signal_Release_Assignment;
+
+   --  precond:  '<='
+   --  postcond: next token
+   --
+   --  [ LRM93 8.4 ]
+   --  signal_assignment_statement ::=
+   --      [ label : ] target <= [ delay_mechanism ] waveform ;
+   --
+   --  [ LRM08 10.5 Signal assignment statement ]
+   --  signal_assignement_statement ::=
+   --      [ label : ] simple_signal_assignement
+   --    | [ label : ] conditional_signal_assignement
+   --    | [ label : ] selected_signal_assignement
+   --
+   --  simple_signal_assignment ::=
+   --      simple_waveform_assignment
+   --    | simple_force_assignment
+   --    | simple_release_assignment
+   function Parse_Signal_Assignment_Statement (Target : Iir) return Iir
+   is
+      Loc : Location_Type;
+   begin
+      Loc := Get_Token_Location;
+
+      --  Skip '<='.
+      Scan;
+
+      case Current_Token is
+         when Tok_Force =>
+            return Parse_Signal_Force_Assignment (Target, Loc);
+         when Tok_Release =>
+            return Parse_Signal_Release_Assignment (Target, Loc);
+         when others =>
+            return Parse_Signal_Waveform_Assignment (Target, Loc);
+      end case;
    end Parse_Signal_Assignment_Statement;
 
    --  precond:  WHEN
diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb
index fb4a55eb8..46bc0890e 100644
--- a/src/vhdl/vhdl-prints.adb
+++ b/src/vhdl/vhdl-prints.adb
@@ -3081,6 +3081,18 @@ package body Vhdl.Prints is
       Disp_End_Label (Ctxt, Stmt, Tok_Loop);
    end Disp_For_Loop_Statement;
 
+   procedure Disp_Force_Mode_Opt (Ctxt : in out Ctxt_Class; Stmt : Iir) is
+   begin
+      if Get_Has_Force_Mode (Stmt) then
+         case Get_Force_Mode (Stmt) is
+            when Iir_Force_In =>
+               Disp_Token (Ctxt, Tok_In);
+            when Iir_Force_Out =>
+               Disp_Token (Ctxt, Tok_Out);
+         end case;
+      end if;
+   end Disp_Force_Mode_Opt;
+
    procedure Disp_Sequential_Statements (Ctxt : in out Ctxt_Class; First : Iir)
    is
       Stmt: Iir;
@@ -3122,6 +3134,25 @@ package body Vhdl.Prints is
                Close_Hbox (Ctxt);
             when Iir_Kind_Selected_Waveform_Assignment_Statement =>
                Disp_Selected_Waveform_Assignment (Ctxt, Stmt);
+            when Iir_Kind_Signal_Force_Assignment_Statement =>
+               Start_Hbox (Ctxt);
+               Disp_Label (Ctxt, Stmt);
+               Print (Ctxt, Get_Target (Stmt));
+               Disp_Token (Ctxt, Tok_Less_Equal);
+               Disp_Token (Ctxt, Tok_Force);
+               Disp_Force_Mode_Opt (Ctxt, Stmt);
+               Print (Ctxt, Get_Expression (Stmt));
+               Disp_Token (Ctxt, Tok_Semi_Colon);
+               Close_Hbox (Ctxt);
+            when Iir_Kind_Signal_Release_Assignment_Statement =>
+               Start_Hbox (Ctxt);
+               Disp_Label (Ctxt, Stmt);
+               Print (Ctxt, Get_Target (Stmt));
+               Disp_Token (Ctxt, Tok_Less_Equal);
+               Disp_Token (Ctxt, Tok_Release);
+               Disp_Force_Mode_Opt (Ctxt, Stmt);
+               Disp_Token (Ctxt, Tok_Semi_Colon);
+               Close_Hbox (Ctxt);
             when Iir_Kind_Variable_Assignment_Statement =>
                Disp_Variable_Assignment (Ctxt, Stmt);
             when Iir_Kind_Conditional_Variable_Assignment_Statement =>
diff --git a/src/vhdl/vhdl-sem_inst.adb b/src/vhdl/vhdl-sem_inst.adb
index 418b3f998..d8ee3bdf6 100644
--- a/src/vhdl/vhdl-sem_inst.adb
+++ b/src/vhdl/vhdl-sem_inst.adb
@@ -368,6 +368,8 @@ package body Vhdl.Sem_Inst is
             Set_Iir_Pure_State (Res, F, Get_Iir_Pure_State (N, F));
          when Type_Iir_Delay_Mechanism =>
             Set_Iir_Delay_Mechanism (Res, F, Get_Iir_Delay_Mechanism (N, F));
+         when Type_Iir_Force_Mode =>
+            Set_Iir_Force_Mode (Res, F, Get_Iir_Force_Mode (N, F));
          when Type_Iir_Predefined_Functions =>
             Set_Iir_Predefined_Functions
               (Res, F, Get_Iir_Predefined_Functions (N, F));
diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb
index 743c38ae6..f6afa2294 100644
--- a/src/vhdl/vhdl-sem_stmts.adb
+++ b/src/vhdl/vhdl-sem_stmts.adb
@@ -308,13 +308,11 @@ package body Vhdl.Sem_Stmts is
       end loop;
    end Check_Aggregate_Target;
 
-   procedure Check_Simple_Signal_Target
-     (Stmt : Iir; Target : Iir; Staticness : Iir_Staticness)
+   --  Return the object of signal TARGET.
+   --  Return Null_Iir if TARGET is not a signal (with an error message).
+   function Check_Simple_Signal_Target_Object (Target : Iir) return Iir
    is
       Target_Object : Iir;
-      Target_Prefix : Iir;
-      Guarded_Target : Tri_State_Type;
-      Targ_Obj_Kind : Iir_Kind;
    begin
       Target_Object := Name_To_Object (Target);
       if Target_Object = Null_Iir then
@@ -323,11 +321,27 @@ package body Vhdl.Sem_Stmts is
          then
             --  Common case: target is not declared.  There was already
             --  an error message for it.
-            return;
+            return Null_Iir;
          end if;
 
          --  Uncommon case: target is not an object (could be a component).
          Error_Msg_Sem (+Target, "target is not a signal name");
+         return Null_Iir;
+      end if;
+
+      return Target_Object;
+   end Check_Simple_Signal_Target_Object;
+
+   procedure Check_Simple_Signal_Target
+     (Stmt : Iir; Target : Iir; Staticness : Iir_Staticness)
+   is
+      Target_Object : Iir;
+      Target_Prefix : Iir;
+      Guarded_Target : Tri_State_Type;
+      Targ_Obj_Kind : Iir_Kind;
+   begin
+      Target_Object := Check_Simple_Signal_Target_Object (Target);
+      if Target_Object = Null_Iir then
          return;
       end if;
 
@@ -852,6 +866,125 @@ package body Vhdl.Sem_Stmts is
       end loop;
    end Sem_Conditional_Expression_Chain;
 
+   procedure Sem_Signal_Force_Release_Assignment (Stmt: Iir)
+   is
+      Target        : Iir;
+      Target_Type   : Iir;
+      Target_Object : Iir;
+      Expr          : Iir;
+      Constrained   : Boolean;
+   begin
+      Target := Get_Target (Stmt);
+
+      --  LRM08 10.5.2 Simple signal assignments
+      --  It is an error if the target of a simple force assignment or a
+      --  simple release assignment is in the form of an aggregate.
+      if Get_Kind (Target) = Iir_Kind_Aggregate then
+         Error_Msg_Sem (+Stmt, "target of %n cannot be an aggregate", +Stmt);
+         return;
+      end if;
+
+      Target := Sem_Expression_Wildcard (Target, Wildcard_Any_Type);
+      Target_Object := Null_Iir;
+      Target_Type := Wildcard_Any_Type;
+      if Target = Null_Iir then
+         --  To avoid spurious errors, assume the target is fully
+         --  constrained.
+         Constrained := True;
+      else
+         Set_Target (Stmt, Target);
+         if Is_Expr_Fully_Analyzed (Target) then
+            Check_Target (Stmt, Target);
+            Target_Type := Get_Type (Target);
+            Target_Object := Check_Simple_Signal_Target_Object (Target);
+            Constrained := Is_Object_Name_Fully_Constrained (Target_Object);
+         else
+            Constrained := False;
+         end if;
+      end if;
+
+      if Target_Object /= Null_Iir then
+         --  LRM08 10.5.2 Simple signal assignments
+         --  If the right-hand side of a simple force assignment or a simple
+         --  release assignment does not specify a force mode, then a default
+         --  force mode is used as follow:
+         if not Get_Has_Force_Mode (Stmt) then
+            case Get_Kind (Target_Object) is
+               when Iir_Kind_Interface_Signal_Declaration =>
+                  case Get_Mode (Target_Object) is
+                     when Iir_In_Mode =>
+                        --  - If the target is a port or signal parameter of
+                        --    mode IN, a force mode IN is used.
+                        Set_Force_Mode (Stmt, Iir_Force_In);
+                     when Iir_Out_Mode
+                       | Iir_Inout_Mode
+                       | Iir_Buffer_Mode =>
+                        --  - If the target is a port of mode OUT, INOUT, or
+                        --    BUFFER, or a signal parameter of mode OUT or
+                        --    INOUT, a force mode OUT is used.
+                        Set_Force_Mode (Stmt, Iir_Force_Out);
+                     when Iir_Linkage_Mode =>
+                        --  FIXME: not specified.
+                        null;
+                     when Iir_Unknown_Mode =>
+                        --  An error.
+                        null;
+                  end case;
+               when Iir_Kind_Signal_Declaration
+                 | Iir_Kind_Guard_Signal_Declaration =>
+                  --  - If the target is not a port or a signal parameter,
+                  --    a force mode of IN is used.
+                  Set_Force_Mode (Stmt, Iir_Force_In);
+               when others =>
+                  Error_Msg_Sem (+Stmt, "target (%n) is not a signal",
+                                 +Get_Base_Name (Target));
+            end case;
+         else
+            --  It is an error if a force mode of OUT is specified and the
+            --  target is a port of mode IN.
+            case Get_Kind (Target_Object) is
+               when Iir_Kind_Interface_Signal_Declaration =>
+                  if Get_Force_Mode (Stmt) = Iir_Force_Out
+                    and then Get_Mode (Target_Object) = Iir_In_Mode
+                  then
+                     Error_Msg_Sem
+                       (+Stmt, "cannot use force OUT for IN port %n",
+                        +Get_Base_Name (Target));
+                  end if;
+               when Iir_Kind_Signal_Declaration
+                 | Iir_Kind_Guard_Signal_Declaration =>
+                  --  FIXME: guard is dubious
+                  null;
+               when others =>
+                  Error_Msg_Sem (+Stmt, "target (%n) is not a signal",
+                                 +Get_Base_Name (Target));
+            end case;
+         end if;
+
+         --  TODO:
+         --  LRM08 10.5.2 Simple signal assignments
+         --  It is an error if a simple force assignemtn schedules a driving
+         --  value force or an effective value force for a member of a
+         --  resolved composite signal.
+      end if;
+
+      if Get_Kind (Stmt) = Iir_Kind_Signal_Force_Assignment_Statement then
+         --  LRM08 10.5.2 Simple signal assignments
+         --  For simple force assignment, the base type of the expression on
+         --  the right-hand side shall be the same as the base type of the
+         --  signal denoted by the target.
+         Expr := Get_Expression (Stmt);
+         Expr := Sem_Expression_Wildcard (Expr, Target_Type, Constrained);
+         if Expr /= Null_Iir then
+            if Is_Expr_Fully_Analyzed (Expr) then
+               Check_Read (Expr);
+               Expr := Eval_Expr_If_Static (Expr);
+            end if;
+            Set_Expression (Stmt, Expr);
+         end if;
+      end if;
+   end Sem_Signal_Force_Release_Assignment;
+
    procedure Sem_Variable_Assignment (Stmt: Iir)
    is
       Target : Iir;
@@ -1563,6 +1696,25 @@ package body Vhdl.Sem_Stmts is
       Sem_Condition_Opt (Stmt);
    end Sem_Break_Statement;
 
+   --  LRM08 11.3 Process statement
+   --  A process statement is said to be a passive process if neither the
+   --  process itself, nor any procedure of which the process is a parent,
+   --  contains a signal assignment statement.  It is an error if a process
+   --  or a concurrent statement, other than a passive process or a concurrent
+   --  statement equivalent to such a process, appears in the entity statement
+   --  part of an entity declaration.
+   procedure Sem_Passive_Statement (Stmt : Iir) is
+   begin
+      if Current_Concurrent_Statement /= Null_Iir
+        and then (Get_Kind (Current_Concurrent_Statement)
+                    in Iir_Kinds_Process_Statement)
+        and then Get_Passive_Flag (Current_Concurrent_Statement)
+      then
+         Error_Msg_Sem
+           (+Stmt, "signal statement forbidden in passive process");
+      end if;
+   end Sem_Passive_Statement;
+
    -- Process is the scope, this is also the process for which drivers can
    -- be created.
    procedure Sem_Sequential_Statements_Internal (First_Stmt : Iir)
@@ -1609,18 +1761,15 @@ package body Vhdl.Sem_Stmts is
                Sem_Sequential_Statements_Internal
                  (Get_Sequential_Statement_Chain (Stmt));
             when Iir_Kind_Simple_Signal_Assignment_Statement
-              | Iir_Kind_Conditional_Signal_Assignment_Statement =>
+               | Iir_Kind_Conditional_Signal_Assignment_Statement =>
+               Sem_Passive_Statement (Stmt);
                Sem_Signal_Assignment (Stmt);
-               if Current_Concurrent_Statement /= Null_Iir and then
-                 Get_Kind (Current_Concurrent_Statement)
-                 in Iir_Kinds_Process_Statement
-                 and then Get_Passive_Flag (Current_Concurrent_Statement)
-               then
-                  Error_Msg_Sem
-                    (+Stmt, "signal statement forbidden in passive process");
-               end if;
+            when Iir_Kind_Signal_Force_Assignment_Statement
+               | Iir_Kind_Signal_Release_Assignment_Statement =>
+               Sem_Passive_Statement (Stmt);
+               Sem_Signal_Force_Release_Assignment (Stmt);
             when Iir_Kind_Variable_Assignment_Statement
-              | Iir_Kind_Conditional_Variable_Assignment_Statement =>
+               | Iir_Kind_Conditional_Variable_Assignment_Statement =>
                Sem_Variable_Assignment (Stmt);
             when Iir_Kind_Return_Statement =>
                Sem_Return_Statement (Stmt);