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| * | Add support for inout gate. Fix #96 | Tristan Gingold | 2020-03-29 | 1 | -3/+39 | |
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| * | Fixed URL of the ghdl/synth Docker image | Rodrigo Alejandro Melo | 2020-03-27 | 1 | -1/+3 | |
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| * | Add min/max gates | Xiretza | 2020-03-22 | 4 | -1/+91 | |
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| * | Move formal tests for gates into single subdirectory | Xiretza | 2020-03-22 | 10 | -10/+1 | |
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| * | Add abs gate (#91) | Xiretza | 2020-03-10 | 5 | -0/+69 | |
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| * | Fix ghdl.cc indentation (#90) | Xiretza | 2020-03-10 | 1 | -168/+169 | |
| | | | | | Switched everything to tabs, since those seemed to be most common. Also added a vim modeline. | |||||
| * | Add test for previous commit. | Tristan Gingold | 2020-03-09 | 2 | -0/+25 | |
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| * | ghdl.cc: avoid infinite recursion due to concatenation. | Tristan Gingold | 2020-03-09 | 1 | -2/+50 | |
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| * | ghdl.cc: refactoring before optimization. | Tristan Gingold | 2020-03-09 | 1 | -25/+26 | |
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| * | ghdl.cc: rewrite help. | Tristan Gingold | 2020-03-01 | 1 | -2/+23 | |
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| * | Show usage with nextpnr instead of arachne-pnr in README (#88) | Xiretza | 2020-02-23 | 1 | -4/+6 | |
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| * | ghdl.cc: adjust after changes in ghdl (for memories). | Tristan Gingold | 2020-02-23 | 1 | -4/+16 | |
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| * | Add a test for issue 1107 | Tristan Gingold | 2020-02-15 | 2 | -0/+24 | |
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| * | Added ECP5 example for Lattice versa devkit (#85) | Martin | 2020-02-14 | 29 | -0/+6692 | |
| | | | | | | | | - LED blinky - Added support for vendor primitives - Workarounds in Verilog for BRAM and primitive wrapping - Docker support Makefiles - openocd support files | |||||
| * | ci: use image with pre-built GHDL (#81) | eine | 2020-01-21 | 2 | -55/+25 | |
| | | | | | | | * ci: use image with pre-built GHDL * ci: execute 'push' workflow on pull_request too | |||||
| * | Make test logs mode consistent: Add OK status. For #79 | Tristan Gingold | 2020-01-20 | 6 | -0/+6 | |
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| * | migrate from Travis to GHA and rework examples (#78) | eine | 2020-01-19 | 53 | -439/+174 | |
| | | | | | | | * migrate from Travis to GHA * rework examples | |||||
| * | add cons_0, div, and umod (#72) | Pepijn de Vos | 2019-12-31 | 1 | -2/+22 | |
| | | | | | | | * add cons_0, [su]div, and umod * Yosys mod is actually remainder semantics | |||||
| * | testsuite: add reproducer for #76 | Tristan Gingold | 2019-12-31 | 2 | -0/+38 | |
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| * | Add more tests for issue#36 | Tristan Gingold | 2019-12-05 | 3 | -0/+71 | |
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| * | Add testcase for #73 | Tristan Gingold | 2019-12-05 | 4 | -0/+63 | |
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| * | handle mem_rd_sync gates. | Tristan Gingold | 2019-12-05 | 1 | -0/+10 | |
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| * | Handle removal of id_output gates. | Tristan Gingold | 2019-12-05 | 1 | -28/+10 | |
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| * | Fix init input for iadff. For #76 | Tristan Gingold | 2019-12-03 | 1 | -1/+1 | |
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| * | Add test for #75 | Tristan Gingold | 2019-12-03 | 2 | -0/+55 | |
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| * | Do not rename ports. Fix #75 | Tristan Gingold | 2019-12-03 | 1 | -8/+9 | |
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| * | Support multiple synthesis. Fix #73 | Tristan Gingold | 2019-12-02 | 1 | -4/+7 | |
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| * | Adjust pr61 testcase to avoid constant propagation. | Tristan Gingold | 2019-11-16 | 1 | -2/+6 | |
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| * | Add testcase from #36 | Tristan Gingold | 2019-11-07 | 2 | -0/+42 | |
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| * | Add testcase for #65 | Tristan Gingold | 2019-11-07 | 4 | -0/+31 | |
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| * | Add testcase from issue 1001 | Tristan Gingold | 2019-11-06 | 3 | -0/+82 | |
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| * | testsuite: reduce verbosity. | Tristan Gingold | 2019-11-06 | 3 | -4/+4 | |
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| * | testsuite: add xfail1 test | Tristan Gingold | 2019-11-05 | 4 | -0/+37 | |
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| * | testsuite: add case for issue 999 | Tristan Gingold | 2019-11-05 | 2 | -0/+43 | |
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| * | testsuite.sh: simplify (only sub sub dirs). | Tristan Gingold | 2019-11-05 | 1 | -21/+3 | |
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| * | testsuite: move pr tests in issues/ | Tristan Gingold | 2019-11-05 | 10 | -17/+28 | |
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| * | testsuite: move tests of examples in a subdir. | Tristan Gingold | 2019-11-05 | 7 | -43/+43 | |
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| * | testsuite: add issue1000 | Tristan Gingold | 2019-11-05 | 2 | -0/+51 | |
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| * | testsuite: add synth_ice40 (from synth), add synth_import. | Tristan Gingold | 2019-11-05 | 1 | -2/+14 | |
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| * | testenv: use abs_topdir for default ghdl.so path. | Tristan Gingold | 2019-11-05 | 1 | -1/+8 | |
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| * | Add testcase for #68 | Tristan Gingold | 2019-11-04 | 2 | -0/+31 | |
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| * | testsuite: it is now possible to run a single test. | Tristan Gingold | 2019-11-04 | 14 | -11/+32 | |
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| * | Add Id_Smod support (#66) | Anton Blanchard | 2019-11-03 | 3 | -0/+27 | |
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| * | add iadff (#67) | Pepijn de Vos | 2019-11-03 | 1 | -1/+8 | |
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| * | rewrite import_memory, directly generate $mem | Tristan Gingold | 2019-11-03 | 1 | -97/+130 | |
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| * | handle formal input ports. | Tristan Gingold | 2019-10-31 | 1 | -5/+31 | |
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| * | Handle Id_Cover_Assert | Tristan Gingold | 2019-10-22 | 1 | -0/+2 | |
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| * | Initial support of memories. | Tristan Gingold | 2019-10-19 | 1 | -18/+152 | |
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| * | Sign extend 32b literals (#61) | Pepijn de Vos | 2019-10-16 | 3 | -4/+78 | |
| | | | | | | | | | | | | | | | | | | | | * sign extend 32b literals * Fix undefined behavior Right shift of a signed values is undefined but does arithemetic shift in practice. However, shifting by more than one int width is also undefined but *wraps around*. This caused bit/log to work because it'd shift mod 32. But it actually cause the UL32 to be wrong because it'd just repeat the value rather than extending. * zero pad unsigned and add signed * add testsuite | |||||
| * | Add Id_Neg support (#63) | Anton Blanchard | 2019-10-16 | 3 | -0/+27 | |
| | | | | | | | | | * Add Id_Neg support * Add testcase for Id_Neg Thanks to Pepijn for the example I based this on. | |||||
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index : iCE40/ghdl-yosys-plugin | |
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