Add Id_Neg support (#63)

* Add Id_Neg support

* Add testcase for Id_Neg

Thanks to Pepijn for the example I based this on.

3 files changed, 27 insertions, 0 deletions

diff --git a/src/ghdl.cc b/src/ghdl.cc
index 91239e5..8d6a287 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -285,6 +285,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
                 case Id_Xnor:
 		case Id_Add:
 		case Id_Sub:
+		case Id_Neg:
 		case Id_Mux2:
 		case Id_Mux4:
 		case Id_Dff:
@@ -397,6 +398,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
 		case Id_Sub:
 			module->addSub(to_str(iname), IN(0), IN(1), OUT(0));
 			break;
+		case Id_Neg:
+			module->addNeg(to_str(iname), IN(0), OUT(0), true);
+			break;
 		case Id_Not:
 			module->addNot(to_str(iname), IN(0), OUT(0));
 			break;
diff --git a/testsuite/pr63/testsuite.sh b/testsuite/pr63/testsuite.sh
new file mode 100755
index 0000000..7be5528
--- /dev/null
+++ b/testsuite/pr63/testsuite.sh
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+run_yosys -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 1111000000000000000000000000000000000000000000000000000000010000 vector.il || exit 1
+
+clean
diff --git a/testsuite/pr63/vector.vhdl b/testsuite/pr63/vector.vhdl
new file mode 100644
index 0000000..568d3f3
--- /dev/null
+++ b/testsuite/pr63/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (
+        u : out signed(63 downto 0)
+        );
+end entity vector;
+
+architecture synth of vector is
+begin
+    u <= -signed'(x"0ffffffffffffff0");
+end synth;