2 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/issue6/testsuite.sh b/testsuite/issue6/testsuite.sh
new file mode 100755
index 0000000..802618d
--- /dev/null
+++ b/testsuite/issue6/testsuite.sh
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+analyze vector.vhdl
+synth vector
+
+clean
diff --git a/testsuite/issue6/vector.vhdl b/testsuite/issue6/vector.vhdl
new file mode 100644
index 0000000..255c0b5
--- /dev/null
+++ b/testsuite/issue6/vector.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (led0: out std_logic);
+end vector;
+
+architecture synth of vector is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+  v <= std_logic_vector'("10101010");
+  led0 <= v(1); --- But led0 <= v(0) works ok
+end synth;