1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/pr64/vector.vhdl b/testsuite/pr64/vector.vhdl
new file mode 100644
index 0000000..c88c117
--- /dev/null
+++ b/testsuite/pr64/vector.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+    port (
+        s : out signed(127 downto 0);
+        u : out unsigned(127 downto 0)
+        );
+end entity vector;
+
+architecture synth of vector is
+begin
+    s <= signed'(x"ffff000000fffff0") * signed'(x"fff0000ffff00000");
+    u <= unsigned'(x"ffff000000fffff0") * unsigned'(x"fff0000ffff00000");
+end synth;