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| author | Tristan Gingold <tgingold@free.fr> | 2020-09-27 09:56:19 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-09-27 09:57:18 +0200 |
| commit | 7d100bbe4c8c8cfbcba13231c47683b52b220b86 (patch) | |
| tree | 190a49e293e60cc866a6f0f8d779fb6a8a2359ce /testsuite | |
| parent | 987f573390666b057b2275ddda3c0f0ef70303c4 (diff) | |
| download | ghdl-yosys-plugin-7d100bbe4c8c8cfbcba13231c47683b52b220b86.tar.gz ghdl-yosys-plugin-7d100bbe4c8c8cfbcba13231c47683b52b220b86.tar.bz2 ghdl-yosys-plugin-7d100bbe4c8c8cfbcba13231c47683b52b220b86.zip | |
testsuite/issues: adjust pr61
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/issues/pr61/vector.vhdl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/testsuite/issues/pr61/vector.vhdl b/testsuite/issues/pr61/vector.vhdl index 4c0f4c9..34274be 100644 --- a/testsuite/issues/pr61/vector.vhdl +++ b/testsuite/issues/pr61/vector.vhdl @@ -15,5 +15,6 @@ begin v1 <= x"0ffffffffffffff0"; v <= v1+(-1); u1 <= x"00ffffffffffff00"; - u <= u1 + (-6); -- +4294967290; +-- u <= u1 + (-6); -- +4294967290; + u <= u1 + 6; end synth; |