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authorTristan Gingold <tgingold@free.fr>2019-11-05 04:44:55 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-05 04:44:55 +0100
commit70acfa684c7752dd836d4bf95c4b7d4d83053592 (patch)
treef171daa26fddc8bf0c6dd438b121c1f3ba76a43e /testsuite/issues/pr63
parent7a7e6050f8db18b7030e05a85cbb378e909d5f7b (diff)
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testsuite: move pr tests in issues/
Diffstat (limited to 'testsuite/issues/pr63')
-rwxr-xr-xtestsuite/issues/pr63/testsuite.sh13
-rw-r--r--testsuite/issues/pr63/vector.vhdl14
2 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/issues/pr63/testsuite.sh b/testsuite/issues/pr63/testsuite.sh
new file mode 100755
index 0000000..cc40f65
--- /dev/null
+++ b/testsuite/issues/pr63/testsuite.sh
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+topdir=../..
+. $topdir/testenv.sh
+
+run_yosys -q -p "ghdl vector.vhdl -e vector; opt; dump -o vector.il"
+
+grep -q 1111000000000000000000000000000000000000000000000000000000010000 vector.il || exit 1
+
+clean
+
+rm vector.il
+echo OK
diff --git a/testsuite/issues/pr63/vector.vhdl b/testsuite/issues/pr63/vector.vhdl
new file mode 100644
index 0000000..568d3f3
--- /dev/null
+++ b/testsuite/issues/pr63/vector.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+ port (
+ u : out signed(63 downto 0)
+ );
+end entity vector;
+
+architecture synth of vector is
+begin
+ u <= -signed'(x"0ffffffffffffff0");
+end synth;