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author | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:19:18 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:19:18 +0200 |
commit | 6340bba68ba501b77c622498250827e4fd631c96 (patch) | |
tree | d92d40620d32c70f0230ca034279a063c3abf636 /testsuite/issues/issue101/counters_3.vhdl | |
parent | ad7cd6279cccb149644ef124b3d46867afa66162 (diff) | |
download | ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.tar.gz ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.tar.bz2 ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.zip |
Add a test for asynchronous reset dff.
Diffstat (limited to 'testsuite/issues/issue101/counters_3.vhdl')
-rw-r--r-- | testsuite/issues/issue101/counters_3.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/issues/issue101/counters_3.vhdl b/testsuite/issues/issue101/counters_3.vhdl new file mode 100644 index 0000000..d2205cb --- /dev/null +++ b/testsuite/issues/issue101/counters_3.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity counters_3 is + port(C, ALOAD : in std_logic; + D : in std_logic_vector(3 downto 0); + Q : out std_logic_vector(3 downto 0)); +end counters_3; + +architecture archi of counters_3 is + signal tmp: std_logic_vector(3 downto 0); +begin + process (C, ALOAD, D) + begin + if (ALOAD='1') then + tmp <= D; + elsif (C'event and C='1') then + tmp <= tmp + 1; + end if; + end process; + + Q <= tmp; + +end archi; |