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authorTristan Gingold <tgingold@free.fr>2020-04-07 08:19:18 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-07 08:19:18 +0200
commit6340bba68ba501b77c622498250827e4fd631c96 (patch)
treed92d40620d32c70f0230ca034279a063c3abf636 /testsuite/issues/issue101/counters_3.vhdl
parentad7cd6279cccb149644ef124b3d46867afa66162 (diff)
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Add a test for asynchronous reset dff.
Diffstat (limited to 'testsuite/issues/issue101/counters_3.vhdl')
-rw-r--r--testsuite/issues/issue101/counters_3.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/issues/issue101/counters_3.vhdl b/testsuite/issues/issue101/counters_3.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity counters_3 is
+ port(C, ALOAD : in std_logic;
+ D : in std_logic_vector(3 downto 0);
+ Q : out std_logic_vector(3 downto 0));
+end counters_3;
+
+architecture archi of counters_3 is
+ signal tmp: std_logic_vector(3 downto 0);
+begin
+ process (C, ALOAD, D)
+ begin
+ if (ALOAD='1') then
+ tmp <= D;
+ elsif (C'event and C='1') then
+ tmp <= tmp + 1;
+ end if;
+ end process;
+
+ Q <= tmp;
+
+end archi;