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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:19:18 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-07 08:19:18 +0200 |
| commit | 6340bba68ba501b77c622498250827e4fd631c96 (patch) | |
| tree | d92d40620d32c70f0230ca034279a063c3abf636 /testsuite/issues/issue101/counters_3.v | |
| parent | ad7cd6279cccb149644ef124b3d46867afa66162 (diff) | |
| download | ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.tar.gz ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.tar.bz2 ghdl-yosys-plugin-6340bba68ba501b77c622498250827e4fd631c96.zip | |
Add a test for asynchronous reset dff.
Diffstat (limited to 'testsuite/issues/issue101/counters_3.v')
| -rw-r--r-- | testsuite/issues/issue101/counters_3.v | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/testsuite/issues/issue101/counters_3.v b/testsuite/issues/issue101/counters_3.v new file mode 100644 index 0000000..bf15520 --- /dev/null +++ b/testsuite/issues/issue101/counters_3.v @@ -0,0 +1,9 @@ +module counters_3 (input wire c, input wire aload, input wire [3:0]d, + output reg [3:0] q); + always @(posedge c, posedge aload) begin + if (aload) + q <= d; + else + q <= q + 1; + end +endmodule |