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authorTristan Gingold <tgingold@free.fr>2020-03-09 18:18:57 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-09 18:18:57 +0100
commit0ccb67f997d2243ef2268811ace3af045fa5481e (patch)
treed49cff67560b4a8882296051e344037d425fc094 /testsuite/issues/bug-loop1/loop1.vhdl
parent71c4894dbf62645eaaab0e0b6d9f1d893577a3c8 (diff)
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Add test for previous commit.
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diff --git a/testsuite/issues/bug-loop1/loop1.vhdl b/testsuite/issues/bug-loop1/loop1.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity loop1 is
+ port (a : std_logic_vector (7 downto 0);
+ o : out std_logic_vector (15 downto 0));
+end;
+
+architecture behav of loop1 is
+ signal s : std_logic_vector (15 downto 0);
+begin
+ s <= a & s (15 downto 8);
+ o <= s;
+end behav;