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authorT. Meissner <programming@goodcleanfun.de>2019-10-07 19:13:46 +0200
committertgingold <tgingold@users.noreply.github.com>2019-10-07 19:13:46 +0200
commitb405a27654f326eb1117c0eda8e7389a64fc5c94 (patch)
tree87867ece999abba761b40ea5d2debdd6018247f4 /testsuite/issue7/testsuite.sh
parentbf8b41da7f0650d93b79447a2a62313b15afc9af (diff)
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testsuite: Add formal tests (#57)
* Add formal tests for shift operations * ci: build ghdl/synth:formal and run test suites in it * add testsuite/formal/testsuite.sh * create testsuite/issues * ci: remove a level of grouping * testenv: fix SYMBIYOSYS * refactor * testsuite/formal/shifts: Add check for shifts > vector length
Diffstat (limited to 'testsuite/issue7/testsuite.sh')
-rwxr-xr-xtestsuite/issue7/testsuite.sh20
1 files changed, 0 insertions, 20 deletions
diff --git a/testsuite/issue7/testsuite.sh b/testsuite/issue7/testsuite.sh
deleted file mode 100755
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--- a/testsuite/issue7/testsuite.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/bin/sh
-
-. ../testenv.sh
-
-run_yosys -Q -q -p "ghdl ref.vhdl -e vector ref; write_verilog ref.v"
-run_yosys -Q -q -p "ghdl ref.vhdl vector.vhdl -e vector synth; write_verilog vector.v"
-
-run_yosys -Q -p '
- read_verilog ref.v
- rename vector ref
-
- read_verilog vector.v
- equiv_make ref vector equiv
-
- hierarchy -top equiv
- equiv_simple
- equiv_status -assert'
-
-clean
-rm -f *.v