Add reproducers for #4

3 files changed, 53 insertions, 0 deletions

diff --git a/testsuite/issue4/counter8.vhdl b/testsuite/issue4/counter8.vhdl
new file mode 100644
index 0000000..2067e23
--- /dev/null
+++ b/testsuite/issue4/counter8.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter8 is
+  port (clk : in std_logic;
+        led0 : out std_logic);
+end counter8;
+
+architecture synth of counter8 is
+  
+begin
+
+  process (clk)
+    variable temp : unsigned (7 downto 0);
+  begin
+    if rising_edge(clk) then
+      temp:= temp + 1;
+      led0 <= temp(0);
+    end if;
+  end process;
+
+end synth;
diff --git a/testsuite/issue4/testsuite.sh b/testsuite/issue4/testsuite.sh
new file mode 100755
index 0000000..9eaedbc
--- /dev/null
+++ b/testsuite/issue4/testsuite.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+. ../testenv.sh
+
+analyze novector.vhdl
+synth no_vector
+
+analyze counter8.vhdl
+synth counter8
+
+analyze vector.vhdl
+synth vector
+
+clean
diff --git a/testsuite/issue4/vector.vhdl b/testsuite/issue4/vector.vhdl
new file mode 100644
index 0000000..de74ea9
--- /dev/null
+++ b/testsuite/issue4/vector.vhdl
@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vector is
+  port (led0: out std_logic);
+end vector;
+
+architecture synth of vector is
+
+signal v : std_logic_vector(7 downto 0);
+
+begin
+  v <= std_logic_vector'("10101010");
+  led0 <= v(0);
+end synth;