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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-07 06:45:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-07 06:45:02 +0200 |
| commit | 768e1f7a45ae1c818eea631d5a8fb79775e34108 (patch) | |
| tree | b42164c61a072c4039926e7864418d6d20a9d35e /src | |
| parent | ef286d8f3e02f7ef5b227f28e66b05122d816129 (diff) | |
| download | ghdl-yosys-plugin-768e1f7a45ae1c818eea631d5a8fb79775e34108.tar.gz ghdl-yosys-plugin-768e1f7a45ae1c818eea631d5a8fb79775e34108.tar.bz2 ghdl-yosys-plugin-768e1f7a45ae1c818eea631d5a8fb79775e34108.zip | |
Add support for smod. Fix #102
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 834553e..c1cab92 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -622,6 +622,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Sdiv: case Id_Udiv: case Id_Srem: + case Id_Smod: case Id_Umod: case Id_Allconst: case Id_Allseq: @@ -821,6 +822,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->addDiv(to_str(iname), IN(0), IN(1), OUT(0), false); break; case Id_Srem: + case Id_Smod: // Yosys modulus usese Verilogs *remainder* behavior // there is no signed modulus operator in Yosys module->addMod(to_str(iname), IN(0), IN(1), OUT(0), true); |