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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:21:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-16 08:21:35 +0200 |
| commit | 62dd5df344c6ff76554920b09dce40641e0faf8c (patch) | |
| tree | ffed27f94f0571b0ad85b8f84f36de68d43a34db /src | |
| parent | e4d180dc9c82d90ef37bd235defd8f1def232b99 (diff) | |
| download | ghdl-yosys-plugin-62dd5df344c6ff76554920b09dce40641e0faf8c.tar.gz ghdl-yosys-plugin-62dd5df344c6ff76554920b09dce40641e0faf8c.tar.bz2 ghdl-yosys-plugin-62dd5df344c6ff76554920b09dce40641e0faf8c.zip | |
ghdl.cc: handle Id_Iinout
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index ef2ddaf..6f7ff3a 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -680,6 +680,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } break; case Id_Inout: + case Id_Iinout: // The wire was created when the port was. break; case Id_Assert: @@ -983,6 +984,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) module->connect(OUT (0), IN (0)); break; case Id_Inout: + case Id_Iinout: // Virtual gate. // Connect input to output. module->connect(OUT(0), IN(0)); |