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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-03 21:33:05 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-03 21:33:31 +0100 |
| commit | 1716e755e14aaaccc60a1bb9fd1e2949c6600c6c (patch) | |
| tree | 7fc3f25f7479af3fc6050be6a8c91c93581bc410 /src | |
| parent | de1a576d22c27df2e6e66335fce81e35b56f3d67 (diff) | |
| download | ghdl-yosys-plugin-1716e755e14aaaccc60a1bb9fd1e2949c6600c6c.tar.gz ghdl-yosys-plugin-1716e755e14aaaccc60a1bb9fd1e2949c6600c6c.tar.bz2 ghdl-yosys-plugin-1716e755e14aaaccc60a1bb9fd1e2949c6600c6c.zip | |
Fix init input for iadff. For #76
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 2a06c53..f34602f 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -694,7 +694,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) // For iadff, the initial value is set on the output // wire. if (id == Id_Iadff) { - net_map[get_output(inst, 0).id]->attributes["\\init"] = IN(2).as_const(); + net_map[get_output(inst, 0).id]->attributes["\\init"] = IN(4).as_const(); } break; case Id_Mux4: |