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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-11-03 17:54:04 +0100 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-11-03 17:54:04 +0100 |
| commit | 0ac58d2a569dae3db5d53c70750c5cb0b535ce8b (patch) | |
| tree | 2c95a759e8f81b4aee9e57b7894da0a84450139f /src | |
| parent | 01001a9cb752dad8ea0a1f451fbf5f4499ccd0b7 (diff) | |
| download | ghdl-yosys-plugin-0ac58d2a569dae3db5d53c70750c5cb0b535ce8b.tar.gz ghdl-yosys-plugin-0ac58d2a569dae3db5d53c70750c5cb0b535ce8b.tar.bz2 ghdl-yosys-plugin-0ac58d2a569dae3db5d53c70750c5cb0b535ce8b.zip | |
add iadff (#67)
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdl.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc index 94a185c..d2d33e6 100644 --- a/src/ghdl.cc +++ b/src/ghdl.cc @@ -491,8 +491,9 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Mux2: case Id_Mux4: case Id_Dff: - case Id_Adff: case Id_Idff: + case Id_Adff: + case Id_Iadff: case Id_Eq: case Id_Ne: case Id_Ult: @@ -684,7 +685,13 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) } break; case Id_Adff: + case Id_Iadff: module->addAdff(to_str(iname), IN(0), IN(2), IN(1), OUT(0), IN(3).as_const()); + // For iadff, the initial value is set on the output + // wire. + if (id == Id_Iadff) { + net_map[get_output(inst, 0).id]->attributes["\\init"] = IN(2).as_const(); + } break; case Id_Mux4: { |