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authorTristan Gingold <tgingold@free.fr>2020-04-23 17:37:44 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-23 17:42:42 +0200
commit0a8a2e95454bde1888edbca50c3894cac5057c23 (patch)
tree192882010c0e3a8da2dfd08ee4549100f1c83b5b /src
parent15371796cfa37b1c624748812da2d7f205e3b03c (diff)
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ghdl.cc: adjust for recent yosys. Fix #107
Diffstat (limited to 'src')
-rw-r--r--src/ghdl.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ghdl.cc b/src/ghdl.cc
index 6dda66d..54fa7e9 100644
--- a/src/ghdl.cc
+++ b/src/ghdl.cc
@@ -567,7 +567,7 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m)
}
Param_Idx nbr_params = get_nbr_params(m);
for (Param_Idx idx = 0; idx < nbr_params; idx++) {
- module->avail_parameters.insert(to_str(get_param_name(m, idx)));
+ module->avail_parameters(to_str(get_param_name(m, idx)));
}
module->fixup_ports();