diff options
author | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
commit | bd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch) | |
tree | 194781d16b082ae259f17dd8dc12b84b04ec7105 /icestick/multi2.vhdl | |
parent | fa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff) | |
download | ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.gz ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.bz2 ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.zip |
Add examples
Diffstat (limited to 'icestick/multi2.vhdl')
-rw-r--r-- | icestick/multi2.vhdl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/icestick/multi2.vhdl b/icestick/multi2.vhdl new file mode 100644 index 0000000..78bf298 --- /dev/null +++ b/icestick/multi2.vhdl @@ -0,0 +1,41 @@ +architecture multi2 of leds is + signal clk_4hz: std_logic; + signal clk_5sec : std_logic; +begin + process (clk) + -- 3_000_000 is 0x2dc6c0 + variable counter : unsigned (23 downto 0); + begin + if rising_edge(clk) then + if counter = 2_999_999 then + counter := x"000000"; + clk_4hz <= '1'; + else + counter := counter + 1; + clk_4hz <= '0'; + end if; + end if; + end process; + + process (clk) + variable counter5 : unsigned (4 downto 0); + begin + if rising_edge (clk) then + clk_5sec <= '0'; + if clk_4hz = '1' then + if counter5 = 19 then + clk_5sec <= '1'; + counter5 := "00000"; + else + counter5 := counter5 + 1; + end if; + end if; + end if; + end process; + + led1 <= clk_5sec; + led2 <= '0'; + led3 <= '0'; + led4 <= '0'; + led5 <= '0'; +end multi2; |