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| author | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
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| committer | Tristan Gingold <tgingold@free.fr> | 2017-02-02 21:35:01 +0100 |
| commit | bd7e5c9457471bb24d825574c9aa3d9a3af63c03 (patch) | |
| tree | 194781d16b082ae259f17dd8dc12b84b04ec7105 /ice40hx8k/leds.vhdl | |
| parent | fa2166d5bbf07ffc764b2e562f1eaf8ae3b4f1b6 (diff) | |
| download | ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.gz ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.tar.bz2 ghdl-yosys-plugin-bd7e5c9457471bb24d825574c9aa3d9a3af63c03.zip | |
Add examples
Diffstat (limited to 'ice40hx8k/leds.vhdl')
| -rw-r--r-- | ice40hx8k/leds.vhdl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/ice40hx8k/leds.vhdl b/ice40hx8k/leds.vhdl new file mode 100644 index 0000000..557585b --- /dev/null +++ b/ice40hx8k/leds.vhdl @@ -0,0 +1,8 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity leds is + port (clk : in std_logic; + led1, led2, led3, led4, led5, led6, led7, led8 : out std_logic); +end leds; |