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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-16 12:20:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-16 12:20:12 +0200 |
| commit | c924837dd7f9164aabb37983fb036ee34a9f1e40 (patch) | |
| tree | 830d0718840d671f87f21ed2832d231c7ffc73d7 | |
| parent | d9ce5d06ecefc5cd3c3a8cbd6cb77afcee5185e9 (diff) | |
| download | ghdl-yosys-plugin-c924837dd7f9164aabb37983fb036ee34a9f1e40.tar.gz ghdl-yosys-plugin-c924837dd7f9164aabb37983fb036ee34a9f1e40.tar.bz2 ghdl-yosys-plugin-c924837dd7f9164aabb37983fb036ee34a9f1e40.zip | |
handle utrunc/strunc. For #33
| -rw-r--r-- | ghdl/ghdl.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index 6e8de96..e92e7e9 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -75,6 +75,12 @@ static RTLIL::SigSpec get_src(std::vector<RTLIL::Wire *> &net_map, Net n) res.extend_u0(get_width(n), false); return res; } + case Id_Utrunc: + case Id_Strunc: + { + RTLIL::SigSpec res = IN(0); + return res.extract(0, get_width(n)); + } case Id_Const_UB32: return SigSpec(get_param_uns32(inst, 0), get_width(n)); case Id_Const_UL32: @@ -299,6 +305,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_UB32: case Id_Const_UL32: case Id_Uextend: + case Id_Utrunc: + case Id_Strunc: case Id_Extract: case Id_Insert: case Id_Concat2: @@ -467,6 +475,8 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Const_UB32: case Id_Const_UL32: case Id_Uextend: + case Id_Utrunc: + case Id_Strunc: case Id_Extract: case Id_Insert: case Id_Concat2: |