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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-07-31 20:38:39 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-07-31 20:38:39 +0200 |
| commit | b6e2889c604c07dc3f4d2fde5aed1b29e1285e25 (patch) | |
| tree | a72ebcf06f8b478cb9b7055f759b66bf1796df92 | |
| parent | 6b23de0fc8afb5e57c876b96f6e32e746202033c (diff) | |
| download | ghdl-yosys-plugin-b6e2889c604c07dc3f4d2fde5aed1b29e1285e25.tar.gz ghdl-yosys-plugin-b6e2889c604c07dc3f4d2fde5aed1b29e1285e25.tar.bz2 ghdl-yosys-plugin-b6e2889c604c07dc3f4d2fde5aed1b29e1285e25.zip | |
add signed compare (#29)
| -rw-r--r-- | ghdl/ghdl.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/ghdl/ghdl.cc b/ghdl/ghdl.cc index b2a2cf7..6926cfd 100644 --- a/ghdl/ghdl.cc +++ b/ghdl/ghdl.cc @@ -271,6 +271,10 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Ule: case Id_Ugt: case Id_Uge: + case Id_Slt: + case Id_Sle: + case Id_Sgt: + case Id_Sge: case Id_Not: case Id_Red_Or: case Id_Red_And: @@ -374,6 +378,18 @@ static void import_module(RTLIL::Design *design, GhdlSynth::Module m) case Id_Uge: module->addGe(to_str(iname), IN(0), IN(1), OUT(0)); break; + case Id_Slt: + module->addLt(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sle: + module->addLe(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sgt: + module->addGt(to_str(iname), IN(0), IN(1), OUT(0), true); + break; + case Id_Sge: + module->addGe(to_str(iname), IN(0), IN(1), OUT(0), true); + break; case Id_Red_Or: module->addReduceOr(to_str(iname), IN(0), OUT(0)); break; |